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1. 发明申请

US20060197566A1 DLL circuit for providing an output signal with a desired phase shift 审中-公开
标题翻译： DLL电路，用于提供具有所需相移的输出信号
公开(公告)号：US20060197566A1
公开(公告)日：2006-09-07
申请号：US11358940
申请日：2006-02-21
申请人： Andreas Jakobs , Andreas Taeuber
发明人： Andreas Jakobs , Andreas Taeuber
IPC分类号： H03L7/06
CPC分类号： H03K5/131
摘要： The present invention relates to a DLL circuit for providing an output signal which is shifted with by a desired phase shift with respect to a periodic input signal. In one embodiment, the DLL Circuit comprises a plurality of delay elements all having the same delay time and being connected in series to form a delay chain, wherein the periodic input signal is applied to the first delay element of the delay chain. The DLL circuit further comprises a detection unit which is connected to the outputs of at least a portion of the delay elements and which is provided to determine which delay element a particular edge of the periodic signal has reached after a predetermined phase progress of the periodic signal, and to generate a corresponding control information which indicates at which delay element the particular edge of the periodic signal has last been determined. The DLL circuit further comprises a selection circuit for selecting one of the delay elements depending on the control information and depending on the desired phase shift and outputting the signal at the output of the selected delay elements as the output signal of the DLL circuit.
摘要翻译：本发明涉及一种用于提供输出信号的DLL电路，该输出信号相对于周期性输入信号被移位期望的相移。在一个实施例中，DLL电路包括多个具有相同延迟时间并被串联连接以形成延迟链的延迟元件，其中周期性输入信号被施加到延迟链的第一延迟元件。 DLL电路还包括检测单元，其连接到延迟元件的至少一部分的输出，并且被提供用于确定在周期信号的预定相位进行之后周期信号的特定边缘已经到达的延迟元件并且产生相应的控制信息，该控制信息指示周期信号的特定边缘最后被确定在哪个延迟元件。 DLL电路还包括一个选择电路，用于根据控制信息选择一个延迟元件，并根据期望的相移，并输出所选延迟元件的输出端的信号作为DLL电路的输出信号。

2. 发明授权

US07707380B2 Memories, method of storing data in memory and method of determining memory cell sector quality 有权
标题翻译：存储器，存储器中存储数据的方法和确定存储器单元扇区质量的方法
公开(公告)号：US07707380B2
公开(公告)日：2010-04-27
申请号：US11541392
申请日：2006-09-29
申请人： Rainer Spielberg , Detlev Richter , Andreas Taeuber , Luca de Ambroggi
发明人： Rainer Spielberg , Detlev Richter , Andreas Taeuber , Luca de Ambroggi
IPC分类号： G06F12/00 , G11C29/00
CPC分类号： G11C29/50 , G11C11/5628 , G11C11/5678 , G11C13/0002 , G11C13/0069 , G11C2029/4402 , G11C2029/5002 , G11C2211/5641
摘要： A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.
摘要翻译：提供了一种将数据存储在存储器中的方法，包括测试多个存储单元扇区中的多个存储单元。每个存储单元扇区包括多个存储单元。根据各存储单元扇区的存储单元的测试结果，每个存储单元扇区被分类为多个质量等级的至少一个质量等级。根据各个存储单元扇区的质量等级，将数据存储在分类的存储单元扇区的存储单元中。

3. 发明申请

US20080237738A1 Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell arrangement; memory module 审中-公开
标题翻译：集成电路，电池，电池布置，集成电路的制造方法，电池装置的制造方法。内存模块
公开(公告)号：US20080237738A1
公开(公告)日：2008-10-02
申请号：US11728970
申请日：2007-03-27
申请人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
发明人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/743 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.
摘要翻译：本发明一般涉及集成电路，单元，单元布置，集成电路的制造方法，单元布置的制造方法和存储器模块。在本发明的实施例中，提供了具有单元的集成电路。电池包括第一源极/漏极区域，第二源极/漏极区域，第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在有源区域上方的栅极绝缘区域，栅极绝缘区域以及在第一源极/漏极区域或第二源极/漏极区域下方的至少一个金属结构。

4. 发明申请

US20080253217A1 Method for accessing a memory cell in an integrated circuit, method of determining a set of word line voltage identifiers in an integrated circuit, method for classifying memory cells in an integrated circuit, method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits 有权
标题翻译：用于访问集成电路中的存储单元的方法，确定集成电路中的一组字线电压标识符的方法，用于对集成电路中的存储单元进行分类的方法，用于确定用于访问存储单元的字线电压的方法集成电路和集成电路
公开(公告)号：US20080253217A1
公开(公告)日：2008-10-16
申请号：US11786765
申请日：2007-04-12
申请人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
发明人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
IPC分类号： G11C8/08 , G11C8/00
CPC分类号： G11C16/08 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C13/0028 , G11C2213/71
摘要： Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits. In an embodiment, a method of accessing a memory cell in an integrated circuit, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes selecting a word line voltage identifier from a pre-stored set of word line voltage identifiers, each one of the pre-stored set of word line voltage identifiers being assigned to at least one of the memory cells in the memory cell field and accessing the memory cell using a word line voltage being dependent on the selected word line voltage identifier.
摘要翻译：本发明的实施例涉及一种用于访问集成电路中的存储单元的方法，确定集成电路中的一组字线电压标识符的方法，用于对集成电路中的存储单元进行分类的方法，用于访问集成电路中的存储单元的字线电压和集成电路。在一个实施例中，一种访问集成电路中的存储单元的方法，其中集成电路具有包括多个存储单元的存储单元区域。该方法包括从预先存储的字线电压标识符组中选择一个字线电压标识符，每一个预先存储的一组字线电压标识符被分配给该存储器单元字段中的至少一个存储单元，使用取决于所选字线电压标识符的字线电压来访问存储器单元。

5. 发明申请

US20080082762A1 Memory systems and methods of operating the memory systems 有权
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080082762A1
公开(公告)日：2008-04-03
申请号：US11529711
申请日：2006-09-28
申请人： Andreas Taeuber , Detlev Richter , Luca de Ambroggi , Rainer Spielberg
发明人： Andreas Taeuber , Detlev Richter , Luca de Ambroggi , Rainer Spielberg
IPC分类号： G06F13/00
CPC分类号： G06F13/4239
摘要： In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.
摘要翻译：在本发明的一个实施例中，提供了一种操作存储器系统的方法，包括同时从存储器系统的多个存储器读取数据，并以存储器系统的I / O端口的输出通道容量从存储器系统输出数据所述存储器系统通过将从所述多个存储器中的至少一些存储器读取的数据的数据总线宽度转换为所述I / O端口的数据总线宽度。

6. 发明授权

US07791940B2 Integrated circuit with switching unit for memory cell coupling, and method for producing an integrated circuit for memory cell coupling 有权
标题翻译：具有用于存储单元耦合的开关单元的集成电路以及用于产生用于存储器单元耦合的集成电路的方法
公开(公告)号：US07791940B2
公开(公告)日：2010-09-07
申请号：US12248505
申请日：2008-10-09
申请人： Andreas Taeuber
发明人： Andreas Taeuber
IPC分类号： G11C16/04
CPC分类号： H01L27/105 , G11C5/063 , H01L27/0207
摘要： An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.
摘要翻译：集成电路具有沿着第一线电耦合的多个第一存储器单元，并且还具有沿第二线电耦合的多个第二存储单元。集成电路还具有开关单元，其具有多个开关元件，该多个开关元件又具有第一触点和第二触点。第一开关元件的第一接触耦合到多个第一存储器单元，并且第二开关元件的第一接触耦合到多个第二存储器单元。此外，第三开关元件的第一接触耦合到第一开关元件的第二触点，并且第四开关元件的第一触点耦合到第二开关元件的第二触点。

7. 发明申请

US20090091976A1 Integrated Circuit with Switching Unit for Memory Cell Coupling, and Method for Producing an Integrated Circuit for Memory Cell Coupling 有权
标题翻译：具有用于存储器单元耦合的开关单元的集成电路，以及用于产生用于存储器单元耦合的集成电路的方法
公开(公告)号：US20090091976A1
公开(公告)日：2009-04-09
申请号：US12248505
申请日：2008-10-09
申请人： Andreas Taeuber
发明人： Andreas Taeuber
IPC分类号： G11C16/04 , G11C5/06 , H01L21/82
CPC分类号： H01L27/105 , G11C5/063 , H01L27/0207
摘要： An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.
摘要翻译：集成电路具有沿着第一线电耦合的多个第一存储器单元，并且还具有沿第二线电耦合的多个第二存储单元。集成电路还具有开关单元，其具有多个开关元件，该多个开关元件又具有第一触点和第二触点。第一开关元件的第一接触耦合到多个第一存储器单元，并且第二开关元件的第一接触耦合到多个第二存储器单元。此外，第三开关元件的第一接触耦合到第一开关元件的第二触点，并且第四开关元件的第一触点耦合到第二开关元件的第二触点。

8. 发明申请

US20080080226A1 Memory system and method of operating the memory system 审中-公开
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080080226A1
公开(公告)日：2008-04-03
申请号：US11526850
申请日：2006-09-25
申请人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
发明人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/5614 , G11C7/1006 , G11C7/22 , G11C11/16 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2207/107 , G11C2211/5641
摘要： A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.
摘要翻译：存储器系统包括多个电阻存储单元区域，至少包括第一电阻存储单元区域和第二电阻存储单元区域，第一电阻存储单元区域形成有多个电阻存储单元，以第一数据存储速度存储数据形成有以低于第一数据存储速度的第二数据存储速度存储数据的多个电阻性存储单元形成的第二电阻性存储单元区域，以及控制器，用于控制多个电阻性存储单元区域之间的数据传输。

9. 发明授权

US06704243B2 Apparatus for generating memory-internal command signals from a memory operation command 有权
标题翻译：用于从存储器操作命令产生存储器内部命令信号的装置
公开(公告)号：US06704243B2
公开(公告)日：2004-03-09
申请号：US10266187
申请日：2002-10-07
申请人： Rex Kho , Paul Schmoelz , Andreas Taeuber
发明人： Rex Kho , Paul Schmoelz , Andreas Taeuber
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/22
摘要： A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal, and an output for applying the memory-internal command signal to a command signal line of the memory system. In the device, the memory-internal command signal is generated at a time which depends on the memory-internal command signal and which is selectively settable and synchronous with a rising or synchronous with a falling edge of the external clock signal.
摘要翻译：一种用于从存储器操作命令产生存储器内部命令信号的装置包括用于接收用于在存储器系统中执行存储器操作的存储器操作命令的命令输入，用于接收外部时钟信号的时钟信号输入和用于施加的输出存储器内部命令信号发送到存储器系统的命令信号线。在该装置中，存储器内部命令信号在取决于存储器内部命令信号的时刻产生，并且其被选择性地设置并且与外部时钟信号的下降沿同步。

10. 发明授权

US07864593B2 Method for classifying memory cells in an integrated circuit 有权
标题翻译：集成电路中存储单元的分类方法
公开(公告)号：US07864593B2
公开(公告)日：2011-01-04
申请号：US11786765
申请日：2007-04-12
申请人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
发明人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C13/0028 , G11C2213/71
摘要： A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.
摘要翻译：提供了一种用于对集成电路中的存储单元进行分类的方法，其中集成电路具有包括多个存储单元的存储单元场。该方法包括为存储器单元的多个子集的存储单元的每个子集确定阈值电压分布; 确定所确定的阈值电压分布是否满足阈值电压准则; 并且取决于确定的阈值电压分布是否满足阈值电压准则，对至少一些未选择的存储器单元进行分类。

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