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1. 发明授权

US06990551B2 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache 失效
公开(公告)号：US06990551B2
公开(公告)日：2006-01-24
申请号：US10917449
申请日：2004-08-13
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Per H. Hammarlund
IPC分类号： G06F12/08
CPC分类号： G06F12/1054 , G06F12/1063 , G06F12/109
摘要： A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.

2. 发明授权

US06560690B2 System and method for employing a global bit for page sharing in a linear-addressed cache 有权
公开(公告)号：US06560690B2
公开(公告)日：2003-05-06
申请号：US09753330
申请日：2000-12-29
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
IPC分类号： G06F1200
CPC分类号： G06F12/1063 , G06F2212/656
摘要： A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.

3. 发明授权

US06675282B2 System and method for employing a global bit for page sharing in a linear-addressed cache 有权
标题翻译：在线性寻址缓存中采用全局位进行页面共享的系统和方法
公开(公告)号：US06675282B2
公开(公告)日：2004-01-06
申请号：US10366200
申请日：2003-02-12
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
IPC分类号： G06F1200
CPC分类号： G06F12/1063 , G06F2212/656
摘要： A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.
摘要翻译：描述用于仅存储由两个或多个进程共享的数据块的一个副本的系统和方法。在一个实施例中，全局/非全局预测器预测由线性地址指定的数据块是由两个或多个进程共享还是不共享。如果预测数据块是非共享的，则引用数据块的线性地址的一部分与唯一的进程标识符组合以形成全局/非全局线性地址。如果数据块被预测为共享，则全局/非全局线性地址是线性地址本身。如果关于数据块是否共享的预测是不正确的，则在计算校正的全局/非全局线性地址时使用数据块是否被共享的实际值。如果由正确预测的全局/非全局线性地址所引用的数据或校正的全局/非全局线性地址驻留在全局/非全局线性寻址高速缓存存储器中，则该数据块被访问和发送到请求处理器。如果由正确预测的全局/非全局线性地址所引用的数据或校正的全局/非全局线性地址不驻留在全局/非全局线性寻址高速缓存存储器中，则由替换策略的数据块由线性地址指定的较高层级的存储设备的数据块替换。

4. 发明授权

US07203825B2 Sharing information to reduce redundancy in hybrid branch prediction 有权
标题翻译：共享信息以减少混合分支预测中的冗余
公开(公告)号：US07203825B2
公开(公告)日：2007-04-10
申请号：US09970485
申请日：2001-10-03
申请人： Herbert H. J. Hum , Stephan J. Jourdan
发明人： Herbert H. J. Hum , Stephan J. Jourdan
IPC分类号： G06F9/32
CPC分类号： G06F9/3848
摘要： A hybrid branch predictor is disclosed. The predictor includes prediction aiding information, a plurality of branch predictors to provide a plurality of branch predictions, a plurality of storage elements to hold less than full extent of the branch predictions, but sharing information among said plurality of storage elements enables extraction of said full extent of the prediction. The predictor also includes a selection mechanism to select a prediction from the plurality of branch predictions.
摘要翻译：公开了一种混合分支预测器。预测器包括预测辅助信息，多个分支预测器以提供多个分支预测，多个存储元件保持小于分支预测的全部范围，但是在所述多个存储元件之间共享信息可以提取所述全部预测的程度。预测器还包括从多个分支预测中选择预测的选择机制。

5. 发明授权

US07360033B2 Hierarchical virtual model of a cache hierarchy in a multiprocessor system 有权
标题翻译：多处理器系统中缓存层次结构的分层虚拟模型
公开(公告)号：US07360033B2
公开(公告)日：2008-04-15
申请号：US11447384
申请日：2006-06-05
申请人： Herbert H. J. Hum , James R. Goodman
发明人： Herbert H. J. Hum , James R. Goodman
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0815 , G06F2212/2542
摘要： The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.
摘要翻译：本文描述的高速缓存一致性协议可用于维护系统的虚拟模型，其中虚拟模型不随系统配置改变而改变。一般来说，虚拟模型是基于系统中的每个节点可以直接与系统中的其他节点通信的假设。在一个实施例中，对于每个高速缓存行，高速缓存行的地址用于将节点指定为“家”节点，将所有其他节点指定为“对等”节点。该协议指定一组消息，用于与线路的家庭节点通信，另一组消息用于与线路的对等节点进行通信。

6. 发明授权

US08171095B2 Speculative distributed conflict resolution for a cache coherency protocol 有权
标题翻译：高速缓存一致性协议的推测性分布式冲突解决方案
公开(公告)号：US08171095B2
公开(公告)日：2012-05-01
申请号：US13047496
申请日：2011-03-14
申请人： Herbert H. J. Hum , James R. Goodman , Robert H. Beers , Rajnish Ghughal
发明人： Herbert H. J. Hum , James R. Goodman , Robert H. Beers , Rajnish Ghughal
IPC分类号： G06F15/16
CPC分类号： G06F12/0831 , G06F12/0826 , G06F2212/622
摘要： A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.
摘要翻译：冲突解决技术提供一致性，使得如果每个节点在该节点已经做出其自己的请求之后监视所有请求，则冲突请求者中的至少一个可以检测所有冲突。如果一行处于“独占”，“修改”或“转发”状态，则在保存唯一副本的节点处解决冲突。冲突解决的胜利者以及可能的失败者将冲突报告给家庭节点，该家庭节点对冲突报告和发出转发指令，以确保所有请求节点最终都接收到所请求的数据。如果所请求的高速缓存行未被缓存或仅在共享状态下存在，则家庭节点提供缓存节点的副本并解决冲突。在一个实施例中，在接收到确认消息之后的所有响应之后的停电时段允许所有冲突节点都知道它们涉及的冲突。

7. 发明授权

US07716409B2 Globally unique transaction identifiers 有权
标题翻译：全球唯一的事务标识符
公开(公告)号：US07716409B2
公开(公告)日：2010-05-11
申请号：US10832606
申请日：2004-04-27
申请人： Herbert H. J. Hum , Aaron T. Spink , Robert G. Blankenship
发明人： Herbert H. J. Hum , Aaron T. Spink , Robert G. Blankenship
IPC分类号： G06F13/14
CPC分类号： G06F15/17381
摘要： In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.
摘要翻译：在本发明的一个实施例中，一种方法包括从具有事务标识符的系统的第一处理器识别到第二处理器的事务。事务标识符可以具有小于或等于两个处理器之间未完成事务的最大数量的值。以这种方式，用于事务标识符的事务字段可以被限制为n位，其中未完成事务的最大数目小于或等于2n。在各种实施例中，与源标识符和家庭节点标识符组合的这种事务标识符可以形成全局唯一的事务标识符。

8. 发明授权

US06922756B2 Forward state for use in cache coherency in a multiprocessor system 失效
标题翻译：在多处理器系统中用于高速缓存一致性的前向状态
公开(公告)号：US06922756B2
公开(公告)日：2005-07-26
申请号：US10325069
申请日：2002-12-19
申请人： Herbert H. J. Hum , James R. Goodman
发明人： Herbert H. J. Hum , James R. Goodman
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0813 , G06F12/0831
摘要： Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that designates a single copy of data from which further copies can be made. A cache line in the F state is used to respond to request for a copy of the cache line. In one embodiment, the newly created copy is placed in the F state and the cache line previously in the F state is put in the Shared (S) state, or the Invalid (I) state. Thus, if the cache line is shared, one shared copy is in the F state and the remaining copies of the cache line are in the S state.
摘要翻译：这里描述了具有五种状态的高速缓存一致性协议：修改，独占，共享，无效和转发（MESIF）。 MESIF高速缓存一致性协议包括转发（F）状态，其指定可以进行进一步复制的数据的单个副本。 F状态的高速缓存行用于响应缓存行副本的请求。在一个实施例中，新创建的副本被置于F状态，并且先前处于F状态的高速缓存行被置于共享（S）状态或无效（I）状态。因此，如果高速缓存行被共享，则一个共享副本处于F状态，并且高速缓存行的剩余副本处于S状态。

9. 发明申请

US20110161451A1 SPECULATIVE DISTRIBUTED CONFLICT RESOLUTION FOR A CACHE COHERENCY PROTOCOL 有权
标题翻译： “高速缓存协议”的分布式分布式冲突解决方案
公开(公告)号：US20110161451A1
公开(公告)日：2011-06-30
申请号：US13047496
申请日：2011-03-14
申请人： Herbert H. J. Hum , James R. Goodman , Robert H. Beers , Rajnish Ghughal
发明人： Herbert H. J. Hum , James R. Goodman , Robert H. Beers , Rajnish Ghughal
IPC分类号： G06F15/16
CPC分类号： G06F12/0831 , G06F12/0826 , G06F2212/622
摘要： A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.
摘要翻译：冲突解决技术提供一致性，使得如果每个节点在该节点已经做出其自己的请求之后监视所有请求，则冲突请求者中的至少一个可以检测所有冲突。如果一行处于“独占”，“修改”或“转发”状态，则在保存唯一副本的节点处解决冲突。冲突解决的胜利者以及可能的失败者将冲突报告给家庭节点，该家庭节点对冲突报告和发出转发指令，以确保所有请求节点最终都接收到所请求的数据。如果所请求的高速缓存行未被缓存或仅在共享状态下存在，则家庭节点提供缓存节点的副本并解决冲突。在一个实施例中，在接收到确认消息之后的所有响应之后的停电时段允许所有冲突节点都知道它们涉及的冲突。

10. 发明授权

US6078992A Dirty line cache 失效
标题翻译：脏线缓存
公开(公告)号：US6078992A
公开(公告)日：2000-06-20
申请号：US985772
申请日：1997-12-05
申请人： Herbert H. J. Hum
发明人： Herbert H. J. Hum
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0897
摘要： A technique for providing a dirty line cache to supplement a cache memory, in order to improve caching performance for a processor in a computer system. A fully-associative cache memory is coupled to operate with a main cache memory at a particular level of the cache hierarchy. The supplemental cache is termed as a dirty line cache, since it only stores dirty cache lines. In the preferred embodiment, the dirty line cache is implemented in a write-out buffer of a write-back or write-through cache.
摘要翻译：用于提供脏线缓存以补充缓存存储器的技术，以便提高计算机系统中处理器的缓存性能。全关联高速缓冲存储器被耦合以与高速缓存层级的特定级别的主高速缓冲存储器一起操作。补充缓存被称为脏行缓存，因为它只存储脏缓存行。在优选实施例中，脏行缓存在写回或高速缓存的写出缓冲器中实现。

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