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1. 发明授权

US06675282B2 System and method for employing a global bit for page sharing in a linear-addressed cache 有权
标题翻译：在线性寻址缓存中采用全局位进行页面共享的系统和方法
公开(公告)号：US06675282B2
公开(公告)日：2004-01-06
申请号：US10366200
申请日：2003-02-12
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
IPC分类号： G06F1200
CPC分类号： G06F12/1063 , G06F2212/656
摘要： A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.
摘要翻译：描述用于仅存储由两个或多个进程共享的数据块的一个副本的系统和方法。在一个实施例中，全局/非全局预测器预测由线性地址指定的数据块是由两个或多个进程共享还是不共享。如果预测数据块是非共享的，则引用数据块的线性地址的一部分与唯一的进程标识符组合以形成全局/非全局线性地址。如果数据块被预测为共享，则全局/非全局线性地址是线性地址本身。如果关于数据块是否共享的预测是不正确的，则在计算校正的全局/非全局线性地址时使用数据块是否被共享的实际值。如果由正确预测的全局/非全局线性地址所引用的数据或校正的全局/非全局线性地址驻留在全局/非全局线性寻址高速缓存存储器中，则该数据块被访问和发送到请求处理器。如果由正确预测的全局/非全局线性地址所引用的数据或校正的全局/非全局线性地址不驻留在全局/非全局线性寻址高速缓存存储器中，则由替换策略的数据块由线性地址指定的较高层级的存储设备的数据块替换。

2. 发明授权

US06560690B2 System and method for employing a global bit for page sharing in a linear-addressed cache 有权
公开(公告)号：US06560690B2
公开(公告)日：2003-05-06
申请号：US09753330
申请日：2000-12-29
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
IPC分类号： G06F1200
CPC分类号： G06F12/1063 , G06F2212/656
摘要： A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.

3. 发明授权

US06990551B2 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache 失效
公开(公告)号：US06990551B2
公开(公告)日：2006-01-24
申请号：US10917449
申请日：2004-08-13
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Per H. Hammarlund
IPC分类号： G06F12/08
CPC分类号： G06F12/1054 , G06F12/1063 , G06F12/109
摘要： A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.

4. 发明授权

US07203825B2 Sharing information to reduce redundancy in hybrid branch prediction 有权
标题翻译：共享信息以减少混合分支预测中的冗余
公开(公告)号：US07203825B2
公开(公告)日：2007-04-10
申请号：US09970485
申请日：2001-10-03
申请人： Herbert H. J. Hum , Stephan J. Jourdan
发明人： Herbert H. J. Hum , Stephan J. Jourdan
IPC分类号： G06F9/32
CPC分类号： G06F9/3848
摘要： A hybrid branch predictor is disclosed. The predictor includes prediction aiding information, a plurality of branch predictors to provide a plurality of branch predictions, a plurality of storage elements to hold less than full extent of the branch predictions, but sharing information among said plurality of storage elements enables extraction of said full extent of the prediction. The predictor also includes a selection mechanism to select a prediction from the plurality of branch predictions.
摘要翻译：公开了一种混合分支预测器。预测器包括预测辅助信息，多个分支预测器以提供多个分支预测，多个存储元件保持小于分支预测的全部范围，但是在所述多个存储元件之间共享信息可以提取所述全部预测的程度。预测器还包括从多个分支预测中选择预测的选择机制。

5. 发明授权

US07529913B2 Late allocation of registers 失效
标题翻译：寄存器后期分配
公开(公告)号：US07529913B2
公开(公告)日：2009-05-05
申请号：US10743065
申请日：2003-12-23
申请人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
发明人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30098 , G06F9/30181 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor.
摘要翻译：本发明的实施例涉及一种用于提供与计算机处理器中的物理寄存器相对应的虚拟标识符的方法和系统。根据实施例，虚拟标识符可以用于在处理器的流水线中的操作期间表示物理寄存器。

6. 发明授权

US07797683B2 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor 有权
标题翻译：从处理器中同时处理的物理线程的数量解耦逻辑线程数
公开(公告)号：US07797683B2
公开(公告)日：2010-09-14
申请号：US10745527
申请日：2003-12-29
申请人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
发明人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
IPC分类号： G06F9/44
CPC分类号： G06F9/485 , G06F9/3851
摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
摘要翻译：管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

7. 发明授权

US07502912B2 Method and apparatus for rescheduling operations in a processor 失效
标题翻译：用于在处理器中重新调度操作的方法和装置
公开(公告)号：US07502912B2
公开(公告)日：2009-03-10
申请号：US10749272
申请日：2003-12-30
申请人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
发明人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting, and sorting the write order of instructions into the scheduler so that the duration the instructions sit idle in the scheduler is minimized. The analyses, prediction, and sorting may be done between an instruction queue and a scheduler by using delay units. The prediction can be based on history (latency, dependency, and resource) or on a general prediction scheme.
摘要翻译：一种用于在处理器中重新调度操作的方法和装置。更具体地说，本发明涉及通过分析，预测和排序指令的写入顺序来最优化地使用处理器中的调度器资源，使得指令在调度器中空闲的持续时间最小化。分析，预测和排序可以通过使用延迟单元在指令队列和调度器之间完成。预测可以基于历史（延迟，依赖和资源）或一般预测方案。

8. 发明申请

US20110060931A1 POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC) 有权
标题翻译：系统芯片（SOC）的功率测量技术
公开(公告)号：US20110060931A1
公开(公告)日：2011-03-10
申请号：US12557263
申请日：2009-09-10
申请人： SIVAKUMAR RADHAKRISHNAN , Sin S. Tan , Stephan J. Jourdan , Lily P. Lool , Yi-Feng Liu
发明人： SIVAKUMAR RADHAKRISHNAN , Sin S. Tan , Stephan J. Jourdan , Lily P. Lool , Yi-Feng Liu
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
摘要翻译：一种能够以各种模式对片上系统进行功率测量的方法和系统。在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。这允许钩子或接口在外部访问片上系统进行测量。例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量，片上片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。另外，由于易于检测故障部件，所以能够提高SOC的整体产量。

9. 发明授权

US07644236B2 Memory cache bank prediction 失效
标题翻译：内存缓存库预测
公开(公告)号：US07644236B2
公开(公告)日：2010-01-05
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

10. 发明授权

US07444457B2 Retrieving data blocks with reduced linear addresses 有权
标题翻译：检索具有减少的线性地址的数据块
公开(公告)号：US07444457B2
公开(公告)日：2008-10-28
申请号：US10743285
申请日：2003-12-23
申请人： Stephan J. Jourdan , Chris E. Yunker , Pierre Michaud
发明人： Stephan J. Jourdan , Chris E. Yunker , Pierre Michaud
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/383 , G06F12/0864
摘要： Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.
摘要翻译：处理地址的系统和方法提供用于接收指令的完整线性地址并减小全线性地址的大小以获得减小的线性地址。如果减少的线性地址对应于标签阵列中的标签，其中标签阵列与数据阵列相关联，则可以从数据阵列检索数据块。缩小的线性地址可使标签阵列的尺寸更小或实现增强的性能。数据阵列可以是高速缓存的分支预测器或高速缓存阵列的预测阵列。

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