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1. 发明授权

US07777300B2 Semiconductor device with capacitor 有权
标题翻译：带电容器的半导体器件
公开(公告)号：US07777300B2
公开(公告)日：2010-08-17
申请号：US11856775
申请日：2007-09-18
申请人： Helmut Tews , Hans-Gerd Jetten , Alexander von Glasow , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Alexander von Glasow , Hans-Joachim Barth
IPC分类号： H01L23/52
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译：一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。

2. 发明申请

US20090073633A1 SEMICONDUCTOR DEVICE WITH CAPACITOR 有权
标题翻译：具有电容器的半导体器件
公开(公告)号：US20090073633A1
公开(公告)日：2009-03-19
申请号：US11856775
申请日：2007-09-18
申请人： Helmut Tews , Hans-Gerd Jetten , Alexander Von Glasow , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Alexander Von Glasow , Hans-Joachim Barth
IPC分类号： H01G4/00 , H01G7/00
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译：一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。

3. 发明授权

US07986023B2 Semiconductor device with inductor 有权
标题翻译：带电感的半导体器件
公开(公告)号：US07986023B2
公开(公告)日：2011-07-26
申请号：US11856089
申请日：2007-09-17
申请人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
IPC分类号： H01L29/00 , H05K7/00
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译：一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。

4. 发明授权

US07816792B2 Semiconductor device with conductive interconnect 有权
标题翻译：具有导电互连的半导体器件
公开(公告)号：US07816792B2
公开(公告)日：2010-10-19
申请号：US11855170
申请日：2007-09-14
申请人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译：一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。

5. 发明申请

US20090072411A1 SEMICONDUCTOR DEVICE WITH CONDUCTIVE INTERCONNECT 有权
标题翻译：具有导电互连的半导体器件
公开(公告)号：US20090072411A1
公开(公告)日：2009-03-19
申请号：US11855170
申请日：2007-09-14
申请人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
IPC分类号： H01L23/48 , H01L21/02
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译：一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。

6. 发明申请

US20090072388A1 SEMICONDUCTOR DEVICE WITH INDUCTOR 有权
标题翻译：带电感器的半导体器件
公开(公告)号：US20090072388A1
公开(公告)日：2009-03-19
申请号：US11856089
申请日：2007-09-17
申请人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
发明人： Helmut Tews , Hans-Gerd Jetten , Hans-Joachim Barth
IPC分类号： H01L23/12 , H01L21/50
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译：一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。

7. 发明授权

US07915132B2 Corresponding capacitor arrangement and method for making the same 有权
标题翻译：相应的电容器布置及其制造方法
公开(公告)号：US07915132B2
公开(公告)日：2011-03-29
申请号：US12562460
申请日：2009-09-18
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L21/20
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译：本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极层。使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

8. 发明申请

US20100001373A1 CORRESPONDING CAPACITOR ARRANGEMENT AND METHOD FOR MAKING THE SAME 有权
标题翻译：相应的电容器布置及其制造方法
公开(公告)号：US20100001373A1
公开(公告)日：2010-01-07
申请号：US12562460
申请日：2009-09-18
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译：本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极层。使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

9. 发明申请

US20060005902A1 Method for production of thin metal-containing layers having low electrical resistance 审中-公开
标题翻译：用于生产具有低电阻的薄金属层的方法
公开(公告)号：US20060005902A1
公开(公告)日：2006-01-12
申请号：US10512016
申请日：2003-04-10
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： C22F1/00
CPC分类号： H01L21/76886
摘要： The invention relates to a method for fabricating thin metal-containing layers (5C) having low electrical resistance, firstly a metal-containing starting layer (5A) having a first grain size being formed on a carrier material (2). Afterwards, a locally delimited thermal region (W) is produced and moved in the metal-containing starting layer (5A) in such a way that a recrystallization of the metal-containing starting layer (5A) is carried out for the purpose of producing the metal-containing layer (5C) having a second grain size, which is enlarged with respect to the first grain size. A metal-containing layer having improved electrical properties is obtained in this way.
摘要翻译：本发明涉及一种用于制造具有低电阻的薄金属层（5C）的方法，首先在载体材料（2）上形成具有第一晶粒尺寸的含金属的起始层（5A）。然后，在含金属的起始层（5A）中产生局部限制的热区（W）并移动，使得含金属的起始层（5A）的再结晶进行为制备具有第二晶粒尺寸的含金属层（5 C），其相对于第一晶粒尺寸扩大。以这种方式获得具有改善的电性能的含金属层。

10. 发明授权

US07635908B2 Corresponding capacitor arrangement and method for making the same 有权
标题翻译：相应的电容器布置及其制造方法
公开(公告)号：US07635908B2
公开(公告)日：2009-12-22
申请号：US11652157
申请日：2007-01-11
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译：本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极层。使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

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