专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06973607B2 Method and apparatus for testing electronic components 失效
标题翻译：用于测试电子部件的方法和装置
公开(公告)号：US06973607B2
公开(公告)日：2005-12-06
申请号：US09998390
申请日：2001-11-29
申请人： Heinz Baier , Robert Francis Berry , Michael Criscolo , Pedro Martin-de-Nicolas , Michael Timothy Saunders , Kanti C. Shah
发明人： Heinz Baier , Robert Francis Berry , Michael Criscolo , Pedro Martin-de-Nicolas , Michael Timothy Saunders , Kanti C. Shah
IPC分类号： G06F11/267 , G01R31/28
CPC分类号： G06F11/2236
摘要： An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.
摘要翻译：一种用于测试一个或多个处理器的装置和方法。该装置和方法提供发布测试用例信息的主计算机。测试用例信息从主计算机使用的架构转换为电子组件所需的体系结构。处理器然后能够执行测试用例。

2. 发明申请

US20080126895A1 MIDDLESOFT COMMANDER 失效
公开(公告)号：US20080126895A1
公开(公告)日：2008-05-29
申请号：US11470478
申请日：2006-09-06
申请人： Heinz Baier , Christopher R. Conley , Brian Flachs , Michael T. Saunders , Steven J. Smolski
发明人： Heinz Baier , Christopher R. Conley , Brian Flachs , Michael T. Saunders , Steven J. Smolski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/2236 , G01R31/318555 , G01R31/318558 , G01R31/318572
摘要： A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.
摘要翻译：一种方法，设备，系统和计算机程序产品，用于实现对JTAG（联合测试动作组）IEEE 1149.1能力设备（或被测系统（SUT））的调试过程的高级控制。 Middlesoft Commander在一个JTAG（或JTAG）POD中提供，它连接到执行调试软件的主机系统和SUT。 POD和SUT之间的通信可以通过桥接POD和SUT之间的连接的一对JTAG接口来实现。 Middlesoft Commander包括代码，使Middlesoft Commander能够将从主机系统（或由主机系统）生成的高级命令（调试数据包）转换为JTAG命令。这些JTAG命令被转发到SUT。 Middlesoft Commander还包括使Middlesoft Commander将从SUT接收到的JTAG数据转换为主机系统可识别的命令的代码。

3. 发明申请

US20080126632A1 STIMULATING AND RECEIVING TEST/DEBUG DATA FROM A SYSTEM UNDER TEST VIA A DRONE CARD PCI BUS 审中-公开
标题翻译：通过DRC卡PCI总线测试和接收来自系统的测试/调试数据
公开(公告)号：US20080126632A1
公开(公告)日：2008-05-29
申请号：US11470507
申请日：2006-09-06
申请人： Heinz Baier , Robert W. Berry , Nicole Criscolo , Brian Flachs , Steven J. Smolski
发明人： Heinz Baier , Robert W. Berry , Nicole Criscolo , Brian Flachs , Steven J. Smolski
IPC分类号： G06F13/00
CPC分类号： G06F11/3648
摘要： A computer-implementable method, system and computer-usable medium for aiding in debugging operations of a System Under Test (SUT) through the use of an external DRONE card is presented. System test software that is running on the SUT “sets aside” debug/status information in a reserved/dedicated Peripheral Component Interface (PCI) section of system memory in the SUT. This information is communicated between the SUT and a DRONE card via a PCI bus. Debug/status information is thus accessed and manipulated by the DRONE card without disturbing (interrupting) normal operations of the SUT.
摘要翻译：介绍了一种用于通过使用外部DRONE卡来帮助被测系统（SUT）进行调试操作的计算机可实现的方法，系统和计算机可用介质。在SUT上运行的系统测试软件在“SUT”的系统内存的保留/专用外设组件接口（PCI）部分中“预留”调试/状态信息。该信息通过PCI总线在SUT和DRONE卡之间通信。调试/状态信息由DRONE卡访问和操作，而不会干扰（中断）SUT的正常操作。

4. 发明授权

US4515027A Unbalance vibrator 失效
标题翻译：不平衡振动器
公开(公告)号：US4515027A
公开(公告)日：1985-05-07
申请号：US454951
申请日：1982-12-30
申请人： Heinz Baier , Hans W. Kurten , Hans-Georg Waschulewski
发明人： Heinz Baier , Hans W. Kurten , Hans-Georg Waschulewski
IPC分类号： B06B1/16 , F16H33/08
CPC分类号： B06B1/164 , B06B1/166 , Y10T74/18344 , Y10T74/18552
摘要： An unbalance vibrator having a shaft 2, with a flyweight 3 rigidly connected thereto, which shaft 2 is mounted in a bearing housing 1, comprises on both sides of this connecting flyweight movable flyweights 5 with flyweight bodies 6 nearly semicircular in cross section and guiding rings 7 nearly semicircular in cross section. The shaft 2 comprises a radial bore on diametrically opposite sides, into which a dog 8 is screwed, and a blind bore 11, into which a locking member 12 is retracted by action of a spring 17. The radial bore 3 and the blind bore 11 are angularly spaced by 90.degree. with respect to the center plane of the flyweight 3 rigidly connected. When the shaft 2 is rotating, the locking member 12 extends from the blind bore 11, such that the movable flyweights 5 are held between the dogs 8 and the locking members 12. The locking members 12 are subjected to hysteresis and are retracted at a rotary speed, which is lower than the loading rotary speed.
摘要翻译：具有轴2的不平衡振动器，其具有刚性地连接到其上的轴3，该轴2安装在轴承壳体1中，包括在该连接的flyweight可动飞轮5的两侧，其中飞行体6的横截面几乎为半圆形，并且导向环 7横截面近半圆形。轴2包括在直径相对的侧面上的径向孔，其中螺钉8被拧入其中，盲孔11通过弹簧17的作用使锁定构件12缩回到其中。径向孔3和盲孔11 相对于刚性连接的飞轮3的中心平面角度间隔90°。当轴2旋转时，锁定构件12从盲孔11延伸，使得可移动的飞轮5保持在挡块8和锁定构件12之间。锁定构件12受到滞后并且以旋转方式缩回速度，低于加载转速。

5. 发明授权

US06976118B1 Method and system for programming FPGAs on PC-cards without additional hardware 失效
标题翻译：无需附加硬件即可在PC卡上编程FPGA的方法和系统
公开(公告)号：US06976118B1
公开(公告)日：2005-12-13
申请号：US09637214
申请日：2000-08-11
申请人： Heinz Baier
发明人： Heinz Baier
IPC分类号： G06F11/00 , G06F9/44 , G06F17/50 , H03K19/173 , G06F12/00
CPC分类号： G06F17/5054
摘要： Programming or updating hardware electronic circuits without manually accessing the circuits is dislcosed. The circuit arrangement includes an EEPROM device, a FPGA device which is accessible via a computer bus system and a MUX element connected between said devices; a PROM device is arranged, inter alia, for comprising control data for proper recognition of the FPGA by the bus system. The MUX element can be controlled to read data from either the PROM device, EEPROM device, or FPGA device. In the method of the present invention, the FPGA is used to program the EEPROM with the schema received from a disk. The MUX is switched to be able to read from the EEPROM and feed the developed schema therein into the FPGA. The PROM is used to deliver the information to the FPGA, which is necessary for the PC-card to be recognized by the BIOS on a first start-up.
摘要翻译：编程或更新硬件电子电路，而不需要手动访问电路就会被忽略。电路装置包括EEPROM器件，可通过计算机总线系统访问的FPGA器件和连接在所述器件之间的MUX元件; PROM装置尤其包括用于包括用于由总线系统正确识别FPGA的控制数据。可以控制MUX元件以从PROM器件，EEPROM器件或FPGA器件读取数据。在本发明的方法中，FPGA用于对从盘接收的模式对EEPROM进行编程。 MUX被切换为能够从EEPROM读取并将其中的开发模式提供到FPGA中。 PROM用于将信息传递给FPGA，这对于PC卡在第一次启动时被BIOS识别是必需的。

6. 发明授权

US4583123A Circuit for a control device for focussing a lens system 失效
标题翻译：用于聚焦透镜系统的控制装置的电路
公开(公告)号：US4583123A
公开(公告)日：1986-04-15
申请号：US704360
申请日：1985-02-22
申请人： Heinz Baier , Michael Kallmeyer , Peter Koepp , Erwin Pfeffer , Martin Schneiderhan
发明人： Heinz Baier , Michael Kallmeyer , Peter Koepp , Erwin Pfeffer , Martin Schneiderhan
IPC分类号： B41J17/30 , B41J17/36 , G02B7/36 , H04N5/232 , H04N3/26
CPC分类号： H04N5/23212 , G02B7/36
摘要： In this circuit, video signals with a continuously increasing or decreasing amplitude are applied to the signal input of a threshold difference comparator at whose reference inputs selectively determined high and low threshold signals are applied. The output of the threshold difference comparator is applied at the first input of a threshold AND gate having a second input connected to a clock. The output of the threshold AND gate supplies a clock pulse sequence which has a duration corresponding with the time during which the input video signal has an amplitude which continuously increases or decreases from one of the threshold reference amplitudes to the other. The clock pulse sequences contained in successive measuring intervals have their respective pulses counted by a counter, and are stored in a buffer. A measurement series is performed corresponding to different focus settings, optimum focus adjustment being achieved when a minimum count of clock pulses in a clock pulse sequence is obtained.
摘要翻译：在该电路中，具有连续增加或减小的幅度的视频信号被施加到阈值差分比较器的信号输入端，其中参考输入选择性地确定施加了高和低阈值信号。阈值差分比较器的输出被施加在具有连接到时钟的第二输入的阈值AND门的第一输入端。阈值与门的输出提供时钟脉冲序列，其具有与输入视频信号具有从阈值参考幅度之一连续增加或减小的幅度的时间相对应的持续时间。连续测量间隔中包含的时钟脉冲序列具有由计数器计数的各自脉冲，并存储在缓冲器中。对应于不同的焦点设置执行测量系列，当获得时钟脉冲序列中的时钟脉冲的最小计数时，实现最佳聚焦调整。

7. 发明授权

US07689865B2 Middlesoft commander 失效
标题翻译：米德尔松指挥官
公开(公告)号：US07689865B2
公开(公告)日：2010-03-30
申请号：US11470478
申请日：2006-09-06
申请人： Heinz Baier , Christopher R. Conley , Brian Flachs , Michael T. Saunders , Steven J. Smolski
发明人： Heinz Baier , Christopher R. Conley , Brian Flachs , Michael T. Saunders , Steven J. Smolski
IPC分类号： G06F11/00
CPC分类号： G06F11/2236 , G01R31/318555 , G01R31/318558 , G01R31/318572
摘要： A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.
摘要翻译：一种方法，设备，系统和计算机程序产品，用于实现对JTAG（联合测试动作组）IEEE 1149.1能力设备（或被测系统（SUT））的调试过程的高级控制。 Middlesoft Commander在一个JTAG（或JTAG）POD中提供，它连接到执行调试软件的主机系统和SUT。 POD和SUT之间的通信可以通过桥接POD和SUT之间的连接的一对JTAG接口来实现。 Middlesoft Commander包括代码，使Middlesoft Commander能够将从主机系统（或由主机系统）生成的高级命令（调试数据包）转换为JTAG命令。这些JTAG命令被转发到SUT。 Middlesoft Commander还包括使Middlesoft Commander将从SUT接收到的JTAG数据转换为主机系统可识别的命令的代码。

8. 发明授权

US4570180A Method for automatic optical inspection 失效
标题翻译：自动光学检测方法
公开(公告)号：US4570180A
公开(公告)日：1986-02-11
申请号：US498333
申请日：1983-05-26
申请人： Heinz Baier , Peter Kopp , Martin Schneiderhan , Hans-Peter Reimann , Hans Rosch , Erwin Pfeffer
发明人： Heinz Baier , Peter Kopp , Martin Schneiderhan , Hans-Peter Reimann , Hans Rosch , Erwin Pfeffer
IPC分类号： G01N21/88 , G01B11/24 , G01N21/956 , G01R31/28 , G01R31/309 , G06T7/00 , H04N7/18
CPC分类号： G06T7/001 , G01B11/24 , G01R31/2806 , G01R31/309 , G06T2207/30141 , G06T2207/30148
摘要： Method and apparatus for automatic optical inspection of a substantially two-dimensional pattern using digital image processing techniques are described. In a first processing step, all regions of a digitized stored image derived from the two-dimensional pattern are scanned for edges or lines, that is, transitions between regions having optically different characteristics. The scanned edge regions are marked in the image storage. In a subsequent second processing step all non-marked regions of the image storage are scanned and tested for the presence of permissible grey levels. A meander-shaped scanning track is used for scanning the edge or lined regions. The apparatus for implementing this method includes special latch circuitry for eliminating the further processing of marked regions, thus increasing the overall speed at which the two-dimensional pattern can be optically inspected.
摘要翻译：描述了使用数字图像处理技术对基本上二维图案进行自动光学检查的方法和装置。在第一处理步骤中，针对边缘或线扫描从二维图案导出的数字化存储的图像的所有区域，即具有光学不同特性的区域之间的转变。扫描的边缘区域被标记在图像存储器中。在随后的第二处理步骤中，图像存储器的所有未标记区域被扫描并测试是否存在允许的灰度级。曲折形扫描轨道用于扫描边缘或内衬区域。用于实现该方法的装置包括用于消除标记区域的进一步处理的特殊锁存电路，从而增加可以对二维图案进行光学检查的整体速度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式