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1. 发明授权

US09342478B2 Processor with reconfigurable architecture including a token network simulating processing of processing elements 有权
标题翻译：具有可重构架构的处理器，包括模拟处理元件处理的令牌网络
公开(公告)号：US09342478B2
公开(公告)日：2016-05-17
申请号：US12581229
申请日：2009-10-19
申请人： Heejun Shim , Sukjin Kim , Hyunchul Park , Scott Mahlke , Yongjun Park
发明人： Heejun Shim , Sukjin Kim , Hyunchul Park , Scott Mahlke , Yongjun Park
IPC分类号： G06F15/78 , G06F13/42
CPC分类号： G06F15/7867 , G06F13/42 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.
摘要翻译：公开了具有可重构架构的处理器中的配置存储器访问技术。具有可重构架构的处理器包括处理元件（PE），配置存储器和令牌网络的阵列。配置存储器存储与控制各个PE的数据流相关联的配置数据。令牌网络从配置存储器读取配置数据，根据读取的配置数据估计PE的数据流，基于估计的数据流从配置存储器读取所需的配置数据，并将所需的配置数据提供给相应的PE。通过令牌网络减少配置存储器访问频率，可能会降低功耗。

2. 发明申请

US20080141012A1 Translation of SIMD instructions in a data processing system 有权
标题翻译： SIMD指令在数据处理系统中的翻译
公开(公告)号：US20080141012A1
公开(公告)日：2008-06-12
申请号：US11905160
申请日：2007-09-27
申请人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
发明人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
IPC分类号： G06F9/318
CPC分类号： G06F9/30054 , G06F9/30032 , G06F9/30036 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3885 , G06F9/3887 , G06F9/45516
摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.
摘要翻译：提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。

3. 发明授权

US07318143B2 Reuseable configuration data 有权
标题翻译：可重复使用的配置数据
公开(公告)号：US07318143B2
公开(公告)日：2008-01-08
申请号：US11044734
申请日：2005-01-28
申请人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/80
CPC分类号： G06F9/3885 , G06F8/433 , G06F8/44 , G06F9/30043 , G06F9/3005 , G06F9/30054 , G06F9/3017 , G06F9/30174 , G06F9/3806 , G06F9/3897
摘要： An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations. The configuration data can be re-used for different operand mappings.
摘要翻译：提供了一种用于执行包括多个独立程序指令的程序的信息处理器。处理器包括可操作以单独执行所述程序的所述单独程序指令的处理逻辑，可操作以存储操作数值的操作数存储器和具有多个功能单元的加速器。加速器通过将所述多个功能单元中的各个功能单元配置为执行与组合操作相关联的特定处理操作，执行与单独程序指令的计算子图相对应的组合操作。加速器根据操作数映射数据执行组合操作，该数据提供组合操作的操作数与所述操作数存储之间的存储位置之间的映射，并且依赖于提供多个功能单元与特定处理操作之间的映射的单独指定的配置数据。配置数据可以重新用于不同的操作数映射。

4. 发明授权

US09965279B2 Recording performance metrics to predict future execution of large instruction sequences on either high or low performance execution circuitry 有权
公开(公告)号：US09965279B2
公开(公告)日：2018-05-08
申请号：US14093042
申请日：2013-11-29
申请人： Shruti Padmanabha , Andrew Lukefahr , Reetuparna Das , Scott Mahlke
发明人： Shruti Padmanabha , Andrew Lukefahr , Reetuparna Das , Scott Mahlke
IPC分类号： G06F9/38 , G06F9/30 , G06F1/32
CPC分类号： G06F9/30058 , G06F1/329 , G06F1/3293 , G06F9/3836 , Y02D10/122 , Y02D10/24
摘要： An apparatus for processing data includes first execution circuitry, such as an out-of-order processor, and second execution circuitry, such as an in-order processor. The first execution circuitry is of higher performance but uses more energy than the second execution circuitry. Control circuitry switches between the first execution circuitry being active and the second execution circuitry being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.

5. 发明授权

US08505002B2 Translation of SIMD instructions in a data processing system 有权
标题翻译： SIMD指令在数据处理系统中的翻译
公开(公告)号：US08505002B2
公开(公告)日：2013-08-06
申请号：US11905160
申请日：2007-09-27
申请人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
发明人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
IPC分类号： G06F9/45
CPC分类号： G06F9/30054 , G06F9/30032 , G06F9/30036 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3885 , G06F9/3887 , G06F9/45516
摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.
摘要翻译：提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。

6. 发明申请

US20120166762A1 COMPUTING APPARATUS AND METHOD BASED ON A RECONFIGURABLE SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURE 审中-公开
标题翻译：基于可重构单个指令多种数据（SIMD）架构的计算机和方法
公开(公告)号：US20120166762A1
公开(公告)日：2012-06-28
申请号：US13179367
申请日：2011-07-08
申请人： Jae Un Park , Suk-Jin Kim , Scott Mahlke , Yong-Jun Park
发明人： Jae Un Park , Suk-Jin Kim , Scott Mahlke , Yong-Jun Park
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/7867 , G06F9/30065 , G06F9/3828 , G06F9/3887 , G06F9/3897 , G06F15/8015
摘要： Provided are a computing apparatus and method based on SIMD architecture capable of supporting various SIMD widths without wasting resources. The computing apparatus includes a plurality of configurable execution cores (CECs) that have a plurality of execution modes, and a controller for detecting a loop region from a program, determining a Single Instruction Multiple Data (SIMD) width for the detected loop region, and determining an execution mode of the processor according to the determined SIMD width.
摘要翻译：提供了一种基于SIMD架构的计算装置和方法，其能够在不浪费资源的情况下支持各种SIMD宽度。计算装置包括具有多个执行模式的多个可配置执行核心（CEC），以及用于检测来自程序的环路区域的控制器，确定检测到的环路区域的单指令多数据（SIMD）宽度，以及根据确定的SIMD宽度确定处理器的执行模式。

7. 发明授权

US09639363B2 Heterogeneity within a processor core 有权
公开(公告)号：US09639363B2
公开(公告)日：2017-05-02
申请号：US14093090
申请日：2013-11-29
申请人： Andrew Lukefahr , Reetuparna Das , Shruti Padmanabha , Scott Mahlke
发明人： Andrew Lukefahr , Reetuparna Das , Shruti Padmanabha , Scott Mahlke
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F9/30189 , G06F1/32 , G06F1/3243 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3891 , Y02D10/124 , Y02D10/152
摘要： A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.

8. 发明授权

US08219885B2 Error detecting and correcting mechanism for a register file 有权
标题翻译：寄存器文件的错误检测和纠正机制
公开(公告)号：US08219885B2
公开(公告)日：2012-07-10
申请号：US12226108
申请日：2006-08-15
申请人： Daryl Wayne Bradley , Jason Andrew Blome , Scott Mahlke
发明人： Daryl Wayne Bradley , Jason Andrew Blome , Scott Mahlke
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/1004
摘要： A data processing system includes a register file having a plurality of registers storing respective register data values and an associated register value cache having a plurality of storage locations storing corresponding cache data values. There are fewer cache data values than registers. When a register is to be read, both the register data value and, if present, a cache data value from a corresponding storage location within the register value cache are read and compared by a comparator. This generates a match signal which indicates if the data values do not match that one of the data values is in error. The match signal stalls the processing and a CRC code initially stored with the cache data value and recalculated based upon the read cache data value are compared to determine whether or not the cache data value has changed since it was stored. If the cache data value has not changed, then it is correct and is output instead of the register data value. Alternatively, if the cache data value has changed, then the register data value is output.
摘要翻译：数据处理系统包括具有存储相应寄存器数据值的多个寄存器的寄存器文件和具有多个存储对应的高速缓存数据值的存储位置的相关联的寄存器值高速缓存。缓存数据值比寄存器少。当要读取寄存器时，寄存器数据值和寄存器值高速缓存中相应存储位置的高速缓存数据值（如果存在）都被比较器读取并比较。这产生一个匹配信号，它指示数据值是否与数据值之一不符。匹配信号使处理停止，并且比较最初存储有高速缓存数据值并基于读取的高速缓存数据值重新计算的CRC码，以确定高速缓存数据值是否已经被存储以来已经改变。如果缓存数据值没有改变，那么它是正确的并且是输出而不是寄存器数据值。或者，如果缓存数据值已经改变，则输出寄存器数据值。

9. 发明授权

US07685404B2 Program subgraph identification 有权
标题翻译：程序子图识别
公开(公告)号：US07685404B2
公开(公告)日：2010-03-23
申请号：US11806907
申请日：2007-06-05
申请人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart David Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F9/00
CPC分类号： G06F8/4441
摘要： An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.
摘要翻译：提供了一种用于在具有程序指令和子图表建议信息的程序的控制下处理数据的装置，其识别与程序内识别的计算子图相对应的程序指令的各个序列。存储器存储由单独的程序指令形成的程序。处理逻辑从所述程序执行相应的单独的程序指令。加速器逻辑响应于到达与子图建议相关联的程序中的执行点，执行对应于子图建议的程序指令序列作为加速操作，而不是执行程序指令序列作为相应的单独的程序指令，其中处理逻辑。

10. 发明授权

US07350055B2 Tightly coupled accelerator 有权
标题翻译：紧耦合加速器
公开(公告)号：US07350055B2
公开(公告)日：2008-03-25
申请号：US11046555
申请日：2005-01-31
申请人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
发明人： Stuart D. Biles , Krisztian Flautner , Scott Mahlke , Nathan Clark
IPC分类号： G06F15/16
CPC分类号： G06F9/3885 , G06F8/44 , G06F9/3005 , G06F9/30054 , G06F9/3806 , G06F9/3836 , G06F9/3897
摘要： An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.
摘要翻译：加速器120紧密耦合到正常执行单元110。执行单元和加速器单元共享作为寄存器文件130的操作数存储器，基于栈的操作数存储或其他操作数存储。操作数也可以在指令本身内作为立即值访问。与计算子图相对应的单独程序指令的顺序保持在程序内，但是可被加速器识别为适合于加速，并且当遇到由加速器而不是由正常执行单元执行时。在这种紧密耦合的布置中，由于系统内缺少寄存器资源，可能会出现问题。本技术规定，在加速器内产生但被确定为不被引用在有关的计算子图之外的至少一些中间操作数值不被写入操作数存储。

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