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1. 发明授权

US09639363B2 Heterogeneity within a processor core 有权
公开(公告)号：US09639363B2
公开(公告)日：2017-05-02
申请号：US14093090
申请日：2013-11-29
申请人： Andrew Lukefahr , Reetuparna Das , Shruti Padmanabha , Scott Mahlke
发明人： Andrew Lukefahr , Reetuparna Das , Shruti Padmanabha , Scott Mahlke
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F9/30189 , G06F1/32 , G06F1/3243 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3891 , Y02D10/124 , Y02D10/152
摘要： A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.

2. 发明申请

US20150154021A1 CONTROL OF SWITCHING BETWEEN EXECUTION MECHANISMS 有权
标题翻译：执行机制之间的切换控制
公开(公告)号：US20150154021A1
公开(公告)日：2015-06-04
申请号：US14093042
申请日：2013-11-29
申请人： Shruti Padmanabha , Andrew Lukefahr , Reetuparna Das , Scott Mahlke
发明人： Shruti Padmanabha , Andrew Lukefahr , Reetuparna Das , Scott Mahlke
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F1/329 , G06F1/3293 , G06F9/3836 , Y02D10/122 , Y02D10/24
摘要： An apparatus 2 for processing data includes first execution circuitry 4, such as an out-of-order processor, and second execution circuitry 6, such as an in-order processor. The first execution circuitry 4 is of higher performance but uses more energy than the second execution circuitry 6. Control circuitry 24 switches between the first execution circuitry 4 being active and the second execution circuitry 6 being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.
摘要翻译：用于处理数据的装置2包括诸如无序处理器的第一执行电路4和诸如按顺序处理器的第二执行电路6。第一执行电路4具有更高的性能，但是比第二执行电路6使用更多的能量。控制电路24在有效的第一执行电路4和有效的第二执行电路6之间切换。控制电路包括预测电路，其被配置为根据最近执行的程序指令序列预测要执行的下一个程序指令序列的预测身份，然后根据该预测的身份来预测相应的预测执行目标是否应该由第一执行电路或第二执行电路执行下一个程序指令序列。

3. 发明授权

US09965279B2 Recording performance metrics to predict future execution of large instruction sequences on either high or low performance execution circuitry 有权
公开(公告)号：US09965279B2
公开(公告)日：2018-05-08
申请号：US14093042
申请日：2013-11-29
申请人： Shruti Padmanabha , Andrew Lukefahr , Reetuparna Das , Scott Mahlke
发明人： Shruti Padmanabha , Andrew Lukefahr , Reetuparna Das , Scott Mahlke
IPC分类号： G06F9/38 , G06F9/30 , G06F1/32
CPC分类号： G06F9/30058 , G06F1/329 , G06F1/3293 , G06F9/3836 , Y02D10/122 , Y02D10/24
摘要： An apparatus for processing data includes first execution circuitry, such as an out-of-order processor, and second execution circuitry, such as an in-order processor. The first execution circuitry is of higher performance but uses more energy than the second execution circuitry. Control circuitry switches between the first execution circuitry being active and the second execution circuitry being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.

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