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1. 发明申请

US20100291741A1 Method of fabricating array substrate 有权
标题翻译：阵列基板的制作方法
公开(公告)号：US20100291741A1
公开(公告)日：2010-11-18
申请号：US12591501
申请日：2009-11-20
申请人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chui Ahn
发明人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chui Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/1274 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

2. 发明授权

US07910414B2 Method of fabricating array substrate 有权
标题翻译：阵列基板的制作方法
公开(公告)号：US07910414B2
公开(公告)日：2011-03-22
申请号：US12591501
申请日：2009-11-20
申请人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chul Ahn
发明人： Hee-Dong Choi , Sang-Gul Lee , Seong-Moh Seo , Jun-Min Lee , Byung-Chul Ahn
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/1274 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

3. 发明申请

US20100117090A1 ARRAY SUBSTRATE INCLUDING THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：包括薄膜晶体管的阵列衬底及其制造方法
公开(公告)号：US20100117090A1
公开(公告)日：2010-05-13
申请号：US12486453
申请日：2009-06-17
申请人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
发明人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
IPC分类号： H01L33/00 , H01L21/336 , H01L21/268
CPC分类号： H01L27/1285 , H01L21/268 , H01L27/1288
摘要： A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
摘要翻译：制造阵列基板的方法包括：形成栅极线和连接到栅极线的栅电极; 在栅极线和栅极绝缘层上形成栅极绝缘层; 在栅电极上的栅极绝缘层上依次形成本征非晶硅图案和杂质掺杂非晶硅图案; 在栅极绝缘层上形成数据线，在掺杂杂质的非晶硅图案上的源电极和漏极之间形成数据线，该数据线与栅极线交叉以限定一个像素区域，以及源极和漏极彼此间隔开; 去除通过源极和漏极暴露的杂质掺杂非晶硅图案的一部分，以限定欧姆接触层; 通过源极和漏极将第一激光束照射到本征非晶硅图案上，以在第一部分的两侧形成包括多晶硅的第一部分和非晶硅的第二部分的有源层; 在数据线上形成钝化层，源电极和漏电极，钝化层具有暴露漏电极的漏极接触孔; 以及在所述像素区域中的钝化层上形成像素电极，所述像素电极通过所述漏极接触孔与所述漏电极连接。

4. 发明授权

US08021937B2 Array substrate including thin film transistor and method of fabricating the same 有权
标题翻译：阵列基板包括薄膜晶体管及其制造方法
公开(公告)号：US08021937B2
公开(公告)日：2011-09-20
申请号：US12486453
申请日：2009-06-17
申请人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
发明人： Hyung-Gu Roh , Byung-Chul Ahn , Hee-Dong Choi , Seong-Moh Seo , Jun-Min Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/1285 , H01L21/268 , H01L27/1288
摘要： A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
摘要翻译：制造阵列基板的方法包括：形成栅极线和连接到栅极线的栅电极; 在栅极线和栅极绝缘层上形成栅极绝缘层; 在栅电极上的栅极绝缘层上依次形成本征非晶硅图案和杂质掺杂非晶硅图案; 在栅极绝缘层上形成数据线，在掺杂杂质的非晶硅图案上的源电极和漏极之间形成数据线，该数据线与栅极线交叉以限定一个像素区域，以及源极和漏极彼此间隔开; 去除通过源极和漏极暴露的杂质掺杂非晶硅图案的一部分，以限定欧姆接触层; 通过源极和漏极将第一激光束照射到本征非晶硅图案上，以在第一部分的两侧形成包括多晶硅的第一部分和非晶硅的第二部分的有源层; 在数据线上形成钝化层，源电极和漏电极，钝化层具有暴露漏电极的漏极接触孔; 以及在所述像素区域中的钝化层上形成像素电极，所述像素电极通过所述漏极接触孔与所述漏电极连接。

5. 发明授权

US08030106B2 Display device and method of manufacturing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US08030106B2
公开(公告)日：2011-10-04
申请号：US12497101
申请日：2009-07-02
申请人： Hee-Dong Choi , Seong-Moh Seo
发明人： Hee-Dong Choi , Seong-Moh Seo
IPC分类号： H01L21/84
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/4908 , H01L29/66765
摘要： A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.
摘要翻译：一种制造显示装置的方法包括：在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成有源层，由外部多晶硅制成的栅电极，由内在的多晶硅; 在所述有源层上形成蚀刻停止层; 在蚀刻停止器上形成彼此间隔开的源极和漏极; 在所述有源层的一侧和所述源极之间以及所述有源层和所述漏电极的相对侧之间形成欧姆接触层; 形成连接到栅电极的栅极线; 并形成跨越栅极线的数据线。

6. 发明授权

US08614462B2 Array substrate for organic electroluminescent device and method of fabricating the same 有权
标题翻译：用于有机电致发光器件的阵列衬底及其制造方法
公开(公告)号：US08614462B2
公开(公告)日：2013-12-24
申请号：US13285584
申请日：2011-10-31
申请人： Hee-Dong Choi , Ki-Sul Cho , Seong-Moh Seo
发明人： Hee-Dong Choi , Ki-Sul Cho , Seong-Moh Seo
IPC分类号： H01L27/118
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1255 , H01L27/3246 , H01L27/3265 , H01L2227/323
摘要： A method of fabricating an array substrate for an organic electroluminescent device includes forming a semiconductor layer of polysilicon in an element region, and a semiconductor pattern of polysilicon in a storage region on a substrate; forming a multiple-layered gate electrode corresponding to a center portion of the semiconductor layer and a first storage electrode corresponding to the semiconductor pattern; performing an impurity-doping to make a portion of the semiconductor layer not covered by the gate electrode into an ohmic contact layer and make the semiconductor pattern into a second storage electrode; forming source and drain electrodes and a third storage electrode corresponding to the first storage electrode; forming a first electrode contacting the drain electrode and a fourth storage electrode corresponding to the third storage electrode.
摘要翻译：一种制造有机电致发光器件用阵列基板的方法包括：在元件区域中形成多晶硅的半导体层，以及在基板上的存储区域中形成多晶硅的半导体图案; 形成对应于所述半导体层的中心部分的多层栅电极和对应于所述半导体图案的第一存储电极; 进行杂质掺杂，使未被栅电极覆盖的半导体层的一部分成为欧姆接触层，并使半导体图案成为第二存储电极; 形成源极和漏极;以及对应于第一存储电极的第三存储电极; 形成与所述漏电极接触的第一电极和对应于所述第三存储电极的第四存储电极。

7. 发明授权

US07833846B1 Array substrate and method of fabricating the same 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US07833846B1
公开(公告)日：2010-11-16
申请号：US12591360
申请日：2009-11-17
申请人： Hee-Dong Choi , Seong-Moh Seo
发明人： Hee-Dong Choi , Seong-Moh Seo
IPC分类号： H01L21/00 , H01L29/04 , H01L21/336 , H01L29/786
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908 , H01L29/66765
摘要： A method of fabricating an array substrate includes forming a buffer layer; forming a gate electrode on the buffer layer, a gate insulating layer on the gate electrode and an active layer on the gate insulating layer, the gate electrode including a bottom pattern, a middle pattern and a top pattern; forming an interlayer insulating layer, the first and second contact holes respectively exposing both sides of the active layer; forming first and second barrier patterns, first and second ohmic contact patterns, a source electrode, a drain, and a data line; forming a first passivation layer including a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; and forming a pixel electrode on the second passivation layer and contacting the drain electrode.
摘要翻译：制造阵列基板的方法包括形成缓冲层; 在所述缓冲层上形成栅电极，在所述栅电极上形成栅极绝缘层，在所述栅极绝缘层上形成有源层，所述栅电极包括底部图案，中间图案和顶部图案; 形成层间绝缘层，所述第一和第二接触孔分别暴露所述有源层的两侧; 形成第一和第二屏障图案，第一和第二欧姆接触图案，源电极，漏极和数据线; 形成包括暴露栅电极的栅极接触孔的第一钝化层; 在所述第一钝化层上形成栅极线，并通过所述栅极接触孔与所述栅电极接触; 在栅极线上形成第二钝化层; 以及在所述第二钝化层上形成像素电极并与所述漏电极接触。

8. 发明授权

US08455874B2 Display device and method of manufacturing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US08455874B2
公开(公告)日：2013-06-04
申请号：US13229272
申请日：2011-09-09
申请人： Hee-Dong Choi , Seong-Moh Seo
发明人： Hee-Dong Choi , Seong-Moh Seo
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/4908 , H01L29/66765
摘要： A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.
摘要翻译：一种制造显示装置的方法包括：在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成有源层，由外部多晶硅制成的栅电极，由内在的多晶硅; 在所述有源层上形成蚀刻停止层; 在蚀刻停止器上形成彼此间隔开的源极和漏极; 在所述有源层的一侧和所述源极之间以及所述有源层和所述漏电极的相对侧之间形成欧姆接触层; 形成连接到栅电极的栅极线; 并形成跨越栅极线的数据线。

9. 发明授权

US08178879B2 Array substrate for display device and method of fabricating the same 有权
标题翻译：用于显示装置的阵列基板及其制造方法
公开(公告)号：US08178879B2
公开(公告)日：2012-05-15
申请号：US12795430
申请日：2010-06-07
申请人： Hee-Dong Choi , Seong-Moh Seo
发明人： Hee-Dong Choi , Seong-Moh Seo
IPC分类号： H01L29/04
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1274
摘要： An array substrate for a display device includes a gate electrode on a substrate; a gate insulating layer on the gate electrode and having the same plane area and the same plane shape as the gate electrode; an active layer on the gate insulating layer and exposing an edge of the gate insulating layer; an interlayer insulating layer on the active layer and including first and second active contact holes, the first and second active contact holes respectively exposing both sides of the active layers; first and second ohmic contact layers contacting the active layer through the first and second active contact holes, respectively; a source electrode on the first ohmic contact layer; a drain electrode on the second ohmic contact layer; a data line on the interlayer insulating layer and connected to the source electrode; a first passivation layer on the source electrode, the drain electrode and the data line, the first passivation layer, the interlayer insulating layer and the gate insulating layer have a first gate contact hole exposing a portion of the gate electrode; a gate line on the first passivation layer and contacting the gate electrode through the first gate contact hole, the gate line crossing the data line; a second passivation layer on the gate line and having a drain contact hole exposing the drain electrode; and a pixel electrode on the second passivation layer and contacting the drain electrode through the contact hole.
摘要翻译：用于显示装置的阵列基板包括在基板上的栅电极; 栅电极上的栅极绝缘层，并且具有与栅电极相同的平面面积和相同的平面形状; 栅极绝缘层上的有源层，并露出栅极绝缘层的边缘; 所述有源层上的层间绝缘层包括第一和第二有源接触孔，所述第一和第二有源接触孔分别暴露有源层的两侧; 第一和第二欧姆接触层分别通过第一和第二有源接触孔与有源层接触; 在第一欧姆接触层上的源电极; 第二欧姆接触层上的漏电极; 在层间绝缘层上的与源电极连接的数据线; 源电极，漏电极和数据线上的第一钝化层，第一钝化层，层间绝缘层和栅极绝缘层具有暴露栅电极的一部分的第一栅极接触孔; 在第一钝化层上的栅极线，并通过第一栅极接触孔与栅电极接触，栅极线与数据线交叉; 栅极线上的第二钝化层，并具有暴露漏电极的漏极接触孔; 以及在所述第二钝化层上的像素电极，并且通过所述接触孔与所述漏电极接触。

10. 发明申请

US20100123138A1 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20100123138A1
公开(公告)日：2010-05-20
申请号：US12497101
申请日：2009-07-02
申请人： Hee-Dong Choi , Seong-Moh Seo
发明人： Hee-Dong Choi , Seong-Moh Seo
IPC分类号： H01L29/786 , H01L21/336 , H01L33/00
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/4908 , H01L29/66765
摘要： A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.
摘要翻译：一种制造显示装置的方法包括：在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成有源层，由外部多晶硅制成的栅电极，由内在的多晶硅; 在所述有源层上形成蚀刻停止层; 在蚀刻停止器上形成彼此间隔开的源极和漏极; 在所述有源层的一侧和所述源极之间以及所述有源层和所述漏电极的相对侧之间形成欧姆接触层; 形成连接到栅电极的栅极线; 并形成跨越栅极线的数据线。

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