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1. 发明授权

US06791861B2 Ferroelectric memory device and a method for driving the same 有权
标题翻译：铁电存储器件及其驱动方法
公开(公告)号：US06791861B2
公开(公告)日：2004-09-14
申请号：US10233429
申请日：2002-09-04
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a plurality of wordlines and a plurality of plate lines, the wordlines and the plate lines being alternately formed at regular intervals in one direction; a plurality of sub bitlines and a plurality of main bitlines, the sub bitlines and the main bitlines alternately formed at regular intervals to cross the wordlines and the plate lines; a plurality of sub cell arrays connected with the wordlines, the sub bitlines and the plate lines, having cells in directions defined by a plurality of rows and columns, the cells in the direction of the rows being arranged every two columns and the cells in the direction of the columns being arranged every two rows, respectively; and switching elements each operating between one of the sub bitlines and one of the main bitlines by an externally applied bitline switch signal of a constant pulse type to selectively connect the sub bitline with the main bitline.
摘要翻译：铁电存储装置包括多个字线和多个板线，字线和板线在一个方向上以规则的间隔交替地形成; 多个子位线和多个主位线，子位线和主位线以规则的间隔交替地形成以跨越字线和板线; 与字线连接的多个子单元阵列，子位线和板线，具有由多个行和列定义的方向上的单元格，行中的单元格每两列布置，并且单元格在柱的方向分别排列成两排; 以及每个在一个子位线和一个主位线之间通过外部施加的恒定脉冲类型的位线开关信号来操作的开关元件，以选择性地将子位线与主位线连接。

2. 发明授权

US06654274B2 Ferroelectric memory and method for driving the same 失效
标题翻译：铁电存储器及其驱动方法
公开(公告)号：US06654274B2
公开(公告)日：2003-11-25
申请号：US10167397
申请日：2002-06-13
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a cell array block having a plurality of sub-cell array blocks regularly arranged in columns and rows, each sub-cell array block includes a plurality of unit cells, a plurality of main bitlines disposed along a first direction corresponding to the sub-cell array blocks in column units, a plurality of sub-bitlines disposed along the first direction in a one-to-one correspondence to the sub-cell array blocks, a plurality of pairs of sub-bitline pull down signal application lines and sub-bitline enable switch signal application lines disposed along a second direction perpendicular to the first direction, each pair corresponding to the sub-cell array block for applying a sub-bitline enable switch signal and a sub-bitline pull down signal, and a plurality of switching control blocks, each corresponding to the sub-cell array block for one of enabling the sub-bitlines selectively in response to the sub-bitline enable switch signal and pulling down the sub-bitlines in response to the sub-bitline pull down signal.
摘要翻译：铁电存储器件包括具有规则排列成列和行的多个子单元阵列块的单元阵列块，每个子单元阵列块包括多个单位单元，沿着与第一方向对应的第一方向布置的多个主位线子单元阵列以列为单位块，与子单元阵列块一一对应地沿着第一方向布置的多个子位线，多个子位线下拉信号施加线对以及沿着垂直于第一方向的第二方向布置的子位线使能开关信号施加线，每对对应于用于施加子位线使能开关信号和子位线下拉信号的子单元阵列块，多个切换控制块，每个对应于子单元阵列块，用于响应于子位线使能切换信号选择性地启用子位线，并且拉下su 响应于子位线下拉信号的b位线。

3. 发明授权

US06498745B2 Circuit for generating timing of reference plate line in nonvolatile ferroelectric memory device and method for driving reference cell 失效
标题翻译：用于在非易失性铁电存储器件中产生参考板线的定时的电路以及用于驱动参考电池的方法
公开(公告)号：US06498745B2
公开(公告)日：2002-12-24
申请号：US09987945
申请日：2001-11-16
申请人： Hee Bok Kang , Hun Woo Kye , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Je Hoon Park
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： In a circuit for generating timing of a reference plate line in the nonvolatile ferroelectric memory device, wherein a nonvolatile ferroelectric memory device having a reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and the reference plate line, the circuit includes a latch circuit receiving a first signal which has the same waveform as that of a chip enable signal and is not delayed and a second signal which has the same waveform as that of the chip enable signal and is delayed for a first period as the chip enable signal is generated, so as to output a low signal only in a delayed period of the second signal, and a delay circuit delaying the first and second signals of the latch circuit to output a low signal to the reference plate line.
摘要翻译：在用于产生非易失性铁电存储器件中的参考板线的定时的电路中，其中具有参考单元的非易失性铁电存储器件包括由参考字线信号控制的开关块，电平启动块，其选择性地启动接收参考均衡器信号之后的开关块的输入端子和并联连接在开关块的输入端子与参考板线路之间的多个铁电电容器，该电路包括接收具有相同信号的第一信号的锁存电路波形作为芯片使能信号的波形并且不被延迟，并且具有与芯片使能信号相同的波形的第二信号，并且在产生芯片使能信号时被延迟第一周期，以便输出低信号仅延迟第二信号的延迟时间，延迟电路使锁存器的第一和第二信号延迟 t将低信号输出到参考板线。

4. 发明授权

US06906975B2 Reference voltage generating circuit of nonvolatile ferroelectric memory device 有权
标题翻译：非易失性铁电存储器件参考电压发生电路
公开(公告)号：US06906975B2
公开(公告)日：2005-06-14
申请号：US10207197
申请日：2002-07-30
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C7/14 , G11C11/22 , G11C7/04
CPC分类号： G11C11/22 , G11C7/14
摘要： A reference voltage generating circuit of a non-volatile ferroelectric memory device includes a temperature compensating control circuit that increases and outputs a level of a signal to a reference capacitor node according to an increase in temperature when a reference control signal is at a high level, a plurality of ferroelectric capacitors connected in parallel, each of first electrodes of the plurality of ferroelectric capacitors are commonly connected to a ground voltage terminal and each of second electrodes of the plurality of ferroelectric capacitors are commonly connected to the reference capacitor node, and a plurality of switching blocks controlled by a reference wordline signal, each having drain terminals commonly connected to the reference capacitor node, source terminals connected to a corresponding bitline.
摘要翻译：非易失性强电介质存储器件的参考电压产生电路包括：温度补偿控制电路，当温度补偿控制信号处于高电平时，根据温度上升，增加信号电平并将其输出到参考电容器节点; 并联连接的多个铁电电容器，多个铁电电容器的每个第一电极共同连接到接地电压端子，并且多个铁电电容器中的每个第二电极共同连接到参考电容器节点，并且多个由参考字线信号控制的开关块，其各自具有共同连接到参考电容器节点的漏极端子，源极端子连接到对应的位线。

5. 发明授权

US06879510B2 Nonvolatile ferroelectric memory device and method for operating the same 有权
标题翻译：非易失性铁电存储器件及其操作方法
公开(公告)号：US06879510B2
公开(公告)日：2005-04-12
申请号：US10286913
申请日：2002-11-04
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C11/22 , G11C5/06
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory device includes a top cell array block having a first plurality of unit cells, each with a pair of first and second top split wordlines, a bottom cell array block provided with a second plurality of unit cells, each having a pair of first and second bottom split wordlines to correspond to the pair of first and second top split wordlines, a top split wordline driver controlling an output signal transmitted to the first and second top split wordlines of the top cell array block, a bottom split wordline driver controlling an output signal transmitted to the first and second bottom split wordlines of the bottom cell array block, a split wordline driver controller outputting first and second split wordline control signals, and a sensing amplifier arranged for each bitline between the top cell array block and the bottom cell array block.
摘要翻译：非易失性铁电存储器件包括具有第一多个单位单元的顶部单元阵列块，每个单元具有一对第一和第二顶部分割字线，底部单元阵列块，其具有第二多个单位单元，每个单元单元具有一对第一和第二底部分割字线对应于一对第一和第二顶部分割字线，顶部分割字线驱动器，控制发送到顶部单元阵列块的第一和第二顶部分离字线的输出信号，底部分离字线驱动器控制发送到底部单元阵列块的第一和第二底部分离字线的输出信号，输出第一和第二分割字线控制信号的分割字线驱动器控制器，以及布置在顶部单元阵列块和底部单元阵列块之间的每个位线的感测放大器单元阵列块。

6. 发明授权

US06836425B2 CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN 有权
标题翻译：非易失性存储器件的编码单元及其操作方法，以及具有编码单元的非易失性存储器件的修复电路及其修复方法
公开(公告)号：US06836425B2
公开(公告)日：2004-12-28
申请号：US10653238
申请日：2003-09-03
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C2900
CPC分类号： G11C29/789 , G11C11/22
摘要： A fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same are disclosed, in which a redundancy time can be reduced and a redundancy algorithm can be changed or added at any time. The fail repair circuit includes: a memory test logic block generating a redundancy active pulse (RAP) if a row address including a fail bit to be repaired is found during test; a power-up sensor generating a power-up pulse if a stable power source voltage is sensed; a first redundancy control block generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block generating an activated coding signal ENW in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block outputting a master signal in response to the coding signal ENW and the first to fifth control signals, programming a fail address in a plurality of redundancy coding cells, and outputting seventh and eighth control signals REN and RPUL to repair the programmed fail address.
摘要翻译：公开了一种非易失性铁电存储器件的故障修复电路及其修复方法，其中可以减少冗余时间，并可随时更改或添加冗余算法。故障修复电路包括：如果在测试期间发现包括要修复的故障位的行地址，则产生冗余有效脉冲（RAP）的存储器测试逻辑块; 如果感测到稳定的电源电压，则产生上电脉冲的上电传感器; 第一冗余控制块，响应于RAP和上电脉冲，产生第一到第五控制信号ENN，ENP，EQN，CPL和PREC以及第六控制信号ENW; 计数器产生通过RAP增加1比特的n比特计数器比特信号以对应于冗余比特数; 冗余计数器解码控制块响应于计数器的计数器位信号和第六控制信号ENW产生激活的编码信号ENW 和第一至第五控制信号输出主信号，对多个冗余编码单元中的故障地址进行编程，并输出第七和第八控制信号REN < 和RPUL 修复编程的失败地址。

7. 发明授权

US06687173B2 Circuit for testing ferroelectric capacitor in FRAM 有权
标题翻译：用于测试FRAM中的铁电电容器的电路
公开(公告)号：US06687173B2
公开(公告)日：2004-02-03
申请号：US10166613
申请日：2002-06-12
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/22 , G11C29/50
摘要： A circuit for testing a ferroelectric capacitor in a FRAM includes: a test pulse signal generating part; a digital test pulse providing part, responsive to the test pulse signal; an n-bit counter, responsive to the digital test pulse signal as a clock signal; a measuring control signal providing part; a write pulse bar signal generating part; an input drive control part for receiving a reference voltage signal, a voltage signal at the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and applying a driving voltage to the second electrode of the ferroelectric capacitor in response to the test pulse signal, and a measured result forwarding part for receiving the reference voltage signal and the voltage signal from the first electrode, and amplifying and forwarding a voltage variation between the electrodes of the ferroelectric capacitor.
摘要翻译：用于测试FRAM中的铁电电容器的电路包括：测试脉冲信号产生部分; 数字测试脉冲提供部分，响应测试脉冲信号; n比特计数器，响应数字测试脉冲信号作为时钟信号; 测量控制信号提供部分; 写脉冲条信号产生部分; 用于接收参考电压信号的输入驱动控制部分，强电介质电容器的第一电极处的电压信号，测量控制信号和写入脉冲条信号，以及向铁电电容器的第二电极施加驱动电压响应于测试脉冲信号，以及测量结果转发部分，用于接收来自第一电极的参考电压信号和电压信号，并且放大并转发铁电电容器的电极之间的电压变化。

8. 发明授权

US06600675B2 Reference circuit in ferroelectric memory and method for driving the same 有权
标题翻译：铁电存储器中的参考电路及其驱动方法
公开(公告)号：US06600675B2
公开(公告)日：2003-07-29
申请号：US10170646
申请日：2002-06-14
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun II Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun II Lee
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A reference circuit in a ferroelectric memory includes a reference plate line and a reference word line adjacently formed in a first direction in correspondence with a cell block including a plurality of unit cells; a plurality of bit lines connected to the unit cells and formed in a second direction; a plurality of parallelly disposed reference capacitors each having a first electrode connected to the reference plate line and a second electrode connected to a storage node SN of a reference cell; an initializing unit connected to the storage node for initializing a level of the reference cell; and a switching block formed between the bit lines and the storage node in correspondence with the bit lines and controlled by signals applied to the reference word line.
摘要翻译：铁电存储器中的参考电路包括与包括多个单元电池的单元块相对应的在第一方向上相邻形成的参考板线和参考字线; 连接到所述单位单元并沿第二方向形成的多个位线; 多个平行布置的参考电容器，每个参考电容器具有连接到参考板线的第一电极和连接到参考单元的存储节点SN的第二电极; 连接到存储节点的初始化单元，用于初始化参考单元的电平; 以及与位线对应地形成在位线和存储节点之间并由施加到参考字线的信号控制的切换块。

9. 发明授权

US06490189B1 Boost voltage generating circuit for nonvolatile ferroelectric memory device and method for generating boost voltage 失效
标题翻译：用于非易失性铁电存储器件的升压产生电路和用于产生升压电压的方法
公开(公告)号：US06490189B1
公开(公告)日：2002-12-03
申请号：US10036369
申请日：2002-01-07
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C5/145
摘要： A boost voltage generating circuit and method for a nonvolatile ferroelectric memory device is disclosed in the present invention. The present invention provides a stable operation when a power source supply voltage region is in a wide power source voltage region, and a layout area for generating a boost voltage is reduced, thereby reducing a chip cost.
摘要翻译：在本发明中公开了一种用于非易失性铁电存储器件的升压电压产生电路和方法。本发明提供电源电压区域处于宽电源电压区域时的稳定动作，并且用于产生升压电压的布局区域减小，从而降低芯片成本。

10. 发明授权

US06868003B2 Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US06868003B2
公开(公告)日：2005-03-15
申请号：US10277735
申请日：2002-10-23
申请人： Hee Bok Kang , Geun Il Lee , Jung Hwan Kim , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Geun Il Lee , Jung Hwan Kim , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C7/00
CPC分类号： G11C11/15
摘要： The present invention discloses a magnetic random access memory comprising MRAM cell groups connected in series in forms of an NAND. The MRAM cell groups comprise magnetic tunnel junctions between word lines and P-N diodes, and memory cells for reading and writing data. In the present invention, the cell size can be reduced by comprising MRAM cell arrays wherein one or more MRAM cells are connected in series in forms of an NAND.
摘要翻译：本发明公开了一种包括以NAND形式串联连接的MRAM单元组的磁随机存取存储器。 MRAM单元组包括字线和P-N二极管之间的磁隧道结，以及用于读取和写入数据的存储单元。在本发明中，通过包括其中一个或多个MRAM单元以NAND形式串联连接的MRAM单元阵列，可以减小单元尺寸。

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