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1. 发明授权

US06791861B2 Ferroelectric memory device and a method for driving the same 有权
标题翻译：铁电存储器件及其驱动方法
公开(公告)号：US06791861B2
公开(公告)日：2004-09-14
申请号：US10233429
申请日：2002-09-04
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a plurality of wordlines and a plurality of plate lines, the wordlines and the plate lines being alternately formed at regular intervals in one direction; a plurality of sub bitlines and a plurality of main bitlines, the sub bitlines and the main bitlines alternately formed at regular intervals to cross the wordlines and the plate lines; a plurality of sub cell arrays connected with the wordlines, the sub bitlines and the plate lines, having cells in directions defined by a plurality of rows and columns, the cells in the direction of the rows being arranged every two columns and the cells in the direction of the columns being arranged every two rows, respectively; and switching elements each operating between one of the sub bitlines and one of the main bitlines by an externally applied bitline switch signal of a constant pulse type to selectively connect the sub bitline with the main bitline.
摘要翻译：铁电存储装置包括多个字线和多个板线，字线和板线在一个方向上以规则的间隔交替地形成; 多个子位线和多个主位线，子位线和主位线以规则的间隔交替地形成以跨越字线和板线; 与字线连接的多个子单元阵列，子位线和板线，具有由多个行和列定义的方向上的单元格，行中的单元格每两列布置，并且单元格在柱的方向分别排列成两排; 以及每个在一个子位线和一个主位线之间通过外部施加的恒定脉冲类型的位线开关信号来操作的开关元件，以选择性地将子位线与主位线连接。

2. 发明授权

US06868003B2 Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US06868003B2
公开(公告)日：2005-03-15
申请号：US10277735
申请日：2002-10-23
申请人： Hee Bok Kang , Geun Il Lee , Jung Hwan Kim , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
发明人： Hee Bok Kang , Geun Il Lee , Jung Hwan Kim , Hun Woo Kye , Duck Ju Kim , Je Hoon Park
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C7/00
CPC分类号： G11C11/15
摘要： The present invention discloses a magnetic random access memory comprising MRAM cell groups connected in series in forms of an NAND. The MRAM cell groups comprise magnetic tunnel junctions between word lines and P-N diodes, and memory cells for reading and writing data. In the present invention, the cell size can be reduced by comprising MRAM cell arrays wherein one or more MRAM cells are connected in series in forms of an NAND.
摘要翻译：本发明公开了一种包括以NAND形式串联连接的MRAM单元组的磁随机存取存储器。 MRAM单元组包括字线和P-N二极管之间的磁隧道结，以及用于读取和写入数据的存储单元。在本发明中，通过包括其中一个或多个MRAM单元以NAND形式串联连接的MRAM单元阵列，可以减小单元尺寸。

3. 发明授权

US06845030B2 Nonvolatile ferroelectric memory device and method of fabricating the same 有权
标题翻译：非易失性铁电存储器件及其制造方法
公开(公告)号：US06845030B2
公开(公告)日：2005-01-18
申请号：US10308098
申请日：2002-12-03
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C5/06 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/115 , G11C8/00
CPC分类号： H01L27/11502 , G11C5/063 , G11C11/22
摘要： A nonvolatile ferroelectric memory device includes a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks include a first plurality of unit cells, a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks include a second plurality of unit cells, a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells, and a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions.
摘要翻译：非易失性铁电存储器件包括沿着第一方向设置的多个顶部阵列块，每个顶部阵列块具有沿垂直于第一方向的第二方向设置的多个顶部子单元阵列块，每个顶部子单元阵列块包括第一多个单位单元，沿着多个顶部阵列块下方的第一方向设置的多个底部阵列块，每个底部阵列块具有沿着第二方向设置的多个底部子单元阵列块，每个底部子单元阵列块包括第二多个单位单元，沿着第二方向延伸并且沿着第一方向以相等的第一间隔布置的多个子位线，每个子位线连接到第一个单元中的一个的至少第一端和第二多个单元电池，以及沿着第二方向延伸并沿着第三方向垂直设置的相等的第一间隔的多个主位线到第一和第二方向。

4. 发明授权

US06775172B2 Nonvolatile ferroelectric memory and method for driving the same 有权
标题翻译：非易失性铁电存储器及其驱动方法
公开(公告)号：US06775172B2
公开(公告)日：2004-08-10
申请号：US10233399
申请日：2002-09-04
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1112
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory includes a top cell array block and a bottom cell array block, each array block having sub cell array blocks, each sub cell array block having a plurality of unit cells; a plurality of main bitlines arranged in one direction in correspondence to a column unit of the sub cell array blocks; a plurality of sub bitlines each connected to one terminal of one of the plurality of unit cells arranged in a same direction as the one direction of the main bitlines; a sense amplifier block having sense amplifiers between the top cell array block and the bottom cell array block, each sense amplifier for amplifying a signal from the main bitline; sub bitline first switch signal application lines and sub bitline second switch signal application lines for controlling connection of the sub bitlines and the main bitlines, sub bitline pull up signal application lines for controlling pull up of the sub bitlines by a self boost operation, and sub bitline pull down signal application lines for selective pull down of the sub bitlines, which are arranged perpendicular to the sub bitlines in correspondence to the sub cell array blocks; a first switch device in each sub cell array block in correspondence to a column direction for operation under control of the sub bitline first switch signal application line; a second switch device in each sub cell array block in correspondence to a column direction for selective transfer of a signal from the sub bitline pull up signal application line to the sub bitline under the control of the sub line second switch signal application line; and, a third switch device in each sub cell array block in correspondence to a column direction for selective pull down of the sub bitline under control of the sub bitline pull down application line.
摘要翻译：非易失性铁电存储器包括顶单元阵列块和底单元阵列块，每个阵列块具有子单元阵列块，每个子单元阵列块具有多个单位单元; 对应于子单元阵列块的列单元沿一个方向布置的多个主位线; 多个子位线，分别连接到与主位线的一个方向相同的方向上布置的多个单位单元中的一个的一个端子; 在顶部单元阵列块和底部单元阵列块之间具有读出放大器的读出放大器块，用于放大来自主位线的信号的每个读出放大器; 子位线第一开关信号施加线和子位线第二开关信号施加线，用于控制子位线和主位线的连接，用于通过自升压操作控制子位线的上拉的副位线上拉信号施加线，以及子位线位线下拉信号施加线，用于与子单元阵列块相对应地垂直于子位线布置的子位线的选择性下拉; 每个子单元阵列块中的对应于在子位线第一开关信号施加线的控制下操作的列方向的第一开关装置; 对应于列方向的每个子单元阵列块中的第二开关装置，用于在子线路第二开关信号施加线的控制下将信号从子位线上拉信号施加线选择性地传送到子位线; 以及在子位线下拉应用行的控制下，与子位线的选择性下拉相对应的列方向的每个子单元阵列块中的第三开关器件。

5. 发明授权

US06754096B2 Apparatus and method for driving ferroelectric memory 有权
标题翻译：用于驱动铁电存储器的装置和方法
公开(公告)号：US06754096B2
公开(公告)日：2004-06-22
申请号：US10320611
申请日：2002-12-17
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C8/06 , G11C8/18
摘要： Disclosed is an apparatus and method for driving a ferroelectric memory that can secure an enough read/write cycle time of a corresponding address during a chip is driven. In a driving circuit to generate an operation pulse for controlling operation of a ferroelectric chip, the ferroelectric memory driving apparatus includes an address latch block for latching a buffered address signal by a feedback cell operation pulse, an address transition detection summation value outputting block for generating an address transition detection pulse by detecting change of an address signal, and for outputting summation of address transition pulses generated by a plurality of addresses, a pulse width extension/control pulse generating block for extending a pulse width of the summation of the address transition pulses and outputting a chip control pulse by using an extended signal, and a cell operation pulse generating block for generating a cell operating pulse with a pulse width required on a read/write chip operation by using the chip control pulse, wherein in an active region of the cell operation pulse corresponding the address, an ATD signal of a different address is not generated.
摘要翻译：公开了一种用于驱动铁电存储器的装置和方法，其可以在驱动芯片期间确保相应地址的足够的读/写周期时间。在用于产生用于控制铁电芯片的操作的操作脉冲的驱动电路中，铁电存储器驱动装置包括用于通过反馈单元操作脉冲来锁存缓冲地址信号的地址锁存块，用于产生的地址转移检测求和值输出块通过检测地址信号的变化并输出由多个地址产生的地址转换脉冲的和的地址转换检测脉冲，用于扩展地址转换脉冲的和的脉冲宽度的脉宽扩展/控制脉冲发生块并通过使用扩展信号输出芯片控制脉冲;以及单元操作脉冲产生模块，用于通过使用芯片控制脉冲产生具有读/写芯片操作所需的脉冲宽度的单元操作脉冲，其中在单元操作脉冲对应的地址，一个ATD信号不同的地址 s不生成。

6. 发明授权

US06845031B2 Nonvolatile ferroelectric memory device and method for driving the same 有权
标题翻译：非易失性铁电存储器件及其驱动方法
公开(公告)号：US06845031B2
公开(公告)日：2005-01-18
申请号：US10326916
申请日：2002-12-23
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory device and a method for driving the same are disclosed, the device and method devised to stabilize the operation processes and reduce the operation time. The nonvolatile ferroelectric memory device includes a cell array block having a plurality of unit cells being controlled by plate lines and wordlines, a plate line driver being positioned on one side of the cell array block to apply a driving signal to the plate lines, a wordline driver being positioned on the other side of the cell array block to apply a driving signal to the wordlines, a plurality of sub bitlines and main bitlines being arranged on the cell array block in the same direction, and switching control blocks controlling signals applied to the sub bitlines and main bitlines.
摘要翻译：公开了一种非易失性铁电存储器件及其驱动方法，该装置和方法旨在稳定操作过程并减少操作时间。非易失性铁电存储器件包括具有由板线和字线控制的多个单位电池的单元阵列块，位于单元阵列块一侧的板线驱动器，以向板线施加驱动信号，字线驱动器位于单元阵列块的另一侧，以将驱动信号施加到字线，多个子位线和主位线沿相同方向布置在单元阵列块上，并且控制块控制施加到单元阵列块的信号次位线和主要位线。

7. 发明授权

US06700812B2 Nonvolatile ferroelectric memory device and method for driving the same 有权
标题翻译：非易失性铁电存储器件及其驱动方法
公开(公告)号：US06700812B2
公开(公告)日：2004-03-02
申请号：US10251848
申请日：2002-09-23
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C11/5657
摘要： A nonvolatile ferroelectric memory device includes a first cell array block and a second cell array block, each divided into an upper part and a lower part; sensing amplifiers arranged one by one on multiple bit lines at a middle portion between the first cell array block and the second cell array block; a data I/O encoder connected to end portions of the multiple bit lines for outputting multi-bit signals by encoding outputs of the sensing amplifiers; and a first reference cell array block and a second reference cell array block arranged between the first cell array block and the data I/O encoder and between the second cell array block and the data I/O encoder.
摘要翻译：非易失性铁电存储器件包括第一单元阵列块和第二单元阵列块，每个分隔成上部和下部; 在第一单元阵列块和第二单元阵列块之间的中间部分的多个位线上逐个布置的感测放大器; 连接到多位线的端部的数据I / O编码器，用于通过对感测放大器的输出进行编码来输出多位信号; 以及布置在第一单元阵列块和数据I / O编码器之间以及第二单元阵列块和数据I / O编码器之间的第一参考单元阵列块和第二参考单元阵列块。

8. 发明授权

US06654274B2 Ferroelectric memory and method for driving the same 失效
标题翻译：铁电存储器及其驱动方法
公开(公告)号：US06654274B2
公开(公告)日：2003-11-25
申请号：US10167397
申请日：2002-06-13
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a cell array block having a plurality of sub-cell array blocks regularly arranged in columns and rows, each sub-cell array block includes a plurality of unit cells, a plurality of main bitlines disposed along a first direction corresponding to the sub-cell array blocks in column units, a plurality of sub-bitlines disposed along the first direction in a one-to-one correspondence to the sub-cell array blocks, a plurality of pairs of sub-bitline pull down signal application lines and sub-bitline enable switch signal application lines disposed along a second direction perpendicular to the first direction, each pair corresponding to the sub-cell array block for applying a sub-bitline enable switch signal and a sub-bitline pull down signal, and a plurality of switching control blocks, each corresponding to the sub-cell array block for one of enabling the sub-bitlines selectively in response to the sub-bitline enable switch signal and pulling down the sub-bitlines in response to the sub-bitline pull down signal.
摘要翻译：铁电存储器件包括具有规则排列成列和行的多个子单元阵列块的单元阵列块，每个子单元阵列块包括多个单位单元，沿着与第一方向对应的第一方向布置的多个主位线子单元阵列以列为单位块，与子单元阵列块一一对应地沿着第一方向布置的多个子位线，多个子位线下拉信号施加线对以及沿着垂直于第一方向的第二方向布置的子位线使能开关信号施加线，每对对应于用于施加子位线使能开关信号和子位线下拉信号的子单元阵列块，多个切换控制块，每个对应于子单元阵列块，用于响应于子位线使能切换信号选择性地启用子位线，并且拉下su 响应于子位线下拉信号的b位线。

9. 发明授权

US06687173B2 Circuit for testing ferroelectric capacitor in FRAM 有权
标题翻译：用于测试FRAM中的铁电电容器的电路
公开(公告)号：US06687173B2
公开(公告)日：2004-02-03
申请号：US10166613
申请日：2002-06-12
申请人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
发明人： Hee Bok Kang , Hun Woo Kye , Duck Ju Kim , Je Hoon Park , Geun Il Lee
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/22 , G11C29/50
摘要： A circuit for testing a ferroelectric capacitor in a FRAM includes: a test pulse signal generating part; a digital test pulse providing part, responsive to the test pulse signal; an n-bit counter, responsive to the digital test pulse signal as a clock signal; a measuring control signal providing part; a write pulse bar signal generating part; an input drive control part for receiving a reference voltage signal, a voltage signal at the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and applying a driving voltage to the second electrode of the ferroelectric capacitor in response to the test pulse signal, and a measured result forwarding part for receiving the reference voltage signal and the voltage signal from the first electrode, and amplifying and forwarding a voltage variation between the electrodes of the ferroelectric capacitor.
摘要翻译：用于测试FRAM中的铁电电容器的电路包括：测试脉冲信号产生部分; 数字测试脉冲提供部分，响应测试脉冲信号; n比特计数器，响应数字测试脉冲信号作为时钟信号; 测量控制信号提供部分; 写脉冲条信号产生部分; 用于接收参考电压信号的输入驱动控制部分，强电介质电容器的第一电极处的电压信号，测量控制信号和写入脉冲条信号，以及向铁电电容器的第二电极施加驱动电压响应于测试脉冲信号，以及测量结果转发部分，用于接收来自第一电极的参考电压信号和电压信号，并且放大并转发铁电电容器的电极之间的电压变化。

10. 发明授权

US06498745B2 Circuit for generating timing of reference plate line in nonvolatile ferroelectric memory device and method for driving reference cell 失效
标题翻译：用于在非易失性铁电存储器件中产生参考板线的定时的电路以及用于驱动参考电池的方法
公开(公告)号：US06498745B2
公开(公告)日：2002-12-24
申请号：US09987945
申请日：2001-11-16
申请人： Hee Bok Kang , Hun Woo Kye , Je Hoon Park
发明人： Hee Bok Kang , Hun Woo Kye , Je Hoon Park
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： In a circuit for generating timing of a reference plate line in the nonvolatile ferroelectric memory device, wherein a nonvolatile ferroelectric memory device having a reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and the reference plate line, the circuit includes a latch circuit receiving a first signal which has the same waveform as that of a chip enable signal and is not delayed and a second signal which has the same waveform as that of the chip enable signal and is delayed for a first period as the chip enable signal is generated, so as to output a low signal only in a delayed period of the second signal, and a delay circuit delaying the first and second signals of the latch circuit to output a low signal to the reference plate line.
摘要翻译：在用于产生非易失性铁电存储器件中的参考板线的定时的电路中，其中具有参考单元的非易失性铁电存储器件包括由参考字线信号控制的开关块，电平启动块，其选择性地启动接收参考均衡器信号之后的开关块的输入端子和并联连接在开关块的输入端子与参考板线路之间的多个铁电电容器，该电路包括接收具有相同信号的第一信号的锁存电路波形作为芯片使能信号的波形并且不被延迟，并且具有与芯片使能信号相同的波形的第二信号，并且在产生芯片使能信号时被延迟第一周期，以便输出低信号仅延迟第二信号的延迟时间，延迟电路使锁存器的第一和第二信号延迟 t将低信号输出到参考板线。

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