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1. 发明申请

US20100217937A1 Data processing apparatus and method 审中-公开
标题翻译：数据处理装置及方法
公开(公告)号：US20100217937A1
公开(公告)日：2010-08-26
申请号：US12379440
申请日：2009-02-20
申请人： Dominic Hugo Symes , Jonathan Sean Callan , Hedley James Francis , Paul Gilbert Meyer
发明人： Dominic Hugo Symes , Jonathan Sean Callan , Hedley James Francis , Paul Gilbert Meyer
IPC分类号： G06F12/12 , G06F12/02
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/383 , G06F12/127 , G06F2212/6028
摘要： A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions. A cache controller is also provided which comprises preload circuitry operable in response to a streaming preload instruction received at the processor to store data values from a main memory into one or more cache lines of the cache memory. The cache controller also comprises identification circuitry operable in response to the streaming preload instruction to identify one or more cache lines of the cache memory for preferential reuse. The cache controller also comprises cache maintenance circuitry operable to implement a cache maintenance operation during which selection of one or more cache lines for reuse is performed having regard to any preferred for reuse identification generated by the identification circuitry for cache lines of the cache memory. In this way, a single streaming preload instruction can be used to trigger both a preload of one or more cache lines of data values into the cache memory, and also to mark for preferential reuse another one or more cache lines of the cache memory.
摘要翻译：描述了一种数据处理装置，其包括可操作以执行指令序列的处理器和具有多个高速缓存行的高速缓存存储器，该多个高速缓存行可操作以在执行指令序列时存储用于由处理器访问的数据值。还提供了一种缓存控制器，其包括预加载电路，该预加载电路响应于在处理器处接收到的流预加载指令而可操作以将来自主存储器的数据值存储到高速缓存存储器的一个或多个高速缓存行。高速缓存控制器还包括可响应于流预加载指令操作的识别电路，以识别用于优先重用的高速缓冲存储器的一个或多个高速缓存行。高速缓存控制器还包括可操作以实现高速缓存维护操作的高速缓存维护电路，在该高速缓存维护操作期间，考虑到用于高速缓冲存储器的高速缓存行的识别电路的识别电路产生的重用标识的任何优选，执行用于重新使用的一个或多个高速缓以这种方式，可以使用单个流预加载指令来将数据值的一个或多个高速缓存行的预加载触发到高速缓冲存储器中，并且还用于标记用于优先重用高速缓冲存储器的另一个或多个高速缓存行。

2. 发明授权

US07426629B2 Processing activity masking in a data processing system 有权
标题翻译：数据处理系统中的处理活动屏蔽
公开(公告)号：US07426629B2
公开(公告)日：2008-09-16
申请号：US10527960
申请日：2003-10-06
申请人： Frederic Claude Marie Piry , Dominic Hugo Symes , Hedley James Francis
发明人： Frederic Claude Marie Piry , Dominic Hugo Symes , Hedley James Francis
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.
摘要翻译：数据处理系统具有这样的机制，即当数据值被存储在数据寄存器中时，另外的数据值存储在一个或多个另外的寄存器中，使得从高到低和从低到高的信号转换的总数量不依赖于正在写入的数据值或先前的数据值而变化。

3. 发明授权

US06831952B2 System, method and computer program for decoding an encoded data stream 失效
标题翻译：用于解码编码数据流的系统，方法和计算机程序
公开(公告)号：US06831952B2
公开(公告)日：2004-12-14
申请号：US09799878
申请日：2001-03-07
申请人： Dominic Hugo Symes , Hedley James Francis
发明人： Dominic Hugo Symes , Hedley James Francis
IPC分类号： H04L2700
CPC分类号： G11B20/10296 , G11B20/12 , H03M13/39 , H03M13/41 , H03M13/4107
摘要： A technique for decoding an encoded data stream representing an original sequence of data bits, each data bit comprising a plurality of codes, each code being dependent on a current data bit and a first predetermined number of preceding data bits in the original sequence. Scores are provided indicating the likelihood that a corresponding state represents the first predetermined number of preceding data bits. The scores are arranged in an initial ordering. A first plurality of score bit slices are stored to collectively represent the initially ordered scores, each score bit slice containing a predetermined bit from each of the scores. The scores are then reordered and a second plurality of score bit slices are stored to collectively represent the reordered scores. By this approach, all the scores are updated simultaneously.
摘要翻译：一种用于解码表示原始数据位序列的编码数据流的技术，每个数据位包括多个代码，每个代码取决于原始序列中的当前数据位和第一预定数量的先前数据位。提供表示指示对应状态表示第一预定数量的先前数据位的可能性。分数按初始排序排列。存储第一多个分数比特片以共同表示最初排序的分数，每个分数比特片包含来自每个分数的预定比特。然后重新排序分数，并且存储第二多个分数比特片以共同表示重新排序的分数。通过这种方法，所有得分都被同时更新。

4. 发明授权

US06584532B1 Branch searching to prioritize received interrupt signals 失效
标题翻译：分支搜索优先接收中断信号
公开(公告)号：US06584532B1
公开(公告)日：2003-06-24
申请号：US09572729
申请日：2000-05-17
申请人： Hedley James Francis , Dominic Hugo Symes
发明人： Hedley James Francis , Dominic Hugo Symes
IPC分类号： G06F1326
CPC分类号： G06F13/26
摘要： A data processing system 2 for identifying the highest priority source signal from a plurality of signals each controlling the setting of a bit of a status word held within a status register 10 using programmable mask words. The mask words are used in a branch search strategy to successively narrow the possibilities for the highest priority bit at each search level until a single bit within the status word is identified corresponding to the highest priority interrupt signal. The programmable masks may be programmed for a particular configuration of the priorities of the respective bits within the status word. The branch search strategy provides a reduced maximum interrupt latency and improved predictability in the interrupt latency.
摘要翻译：一种数据处理系统2，用于从多个信号中识别最高优先级的源信号，每个信号使用可编程掩码字来控制状态寄存器10中保持的状态字的位的设置。在分支搜索策略中使用掩码字来连续地缩小每个搜索级别的最高优先级位的可能性，直到状态字中的单个位被识别为对应于最高优先级的中断信号。可编程掩模可以被编程用于状态字内各个位的优先级的特定配置。分支搜索策略提供了减少的最大中断延迟并提高了中断延迟的可预测性。

5. 发明授权

US09557994B2 Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number 有权
标题翻译：数据处理装置和方法，用于执行N为奇数的N次交织和解交织操作
公开(公告)号：US09557994B2
公开(公告)日：2017-01-31
申请号：US12588412
申请日：2009-10-14
申请人： Dominic Hugo Symes , Simon Andrew Ford
发明人： Dominic Hugo Symes , Simon Andrew Ford
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F7/48
CPC分类号： G06F9/30021 , G06F7/4812 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30189 , G06F9/345 , G06F9/382 , G06F9/3832 , G06F9/3873 , G06F9/3887 , G06F2207/3828
摘要： A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques.
摘要翻译：提供了一种执行重排操作的数据处理装置和方法。数据处理装置具有具有多个寄存器的寄存器数据存储器，每个寄存器存储多个数据元素。处理电路响应于控制信号来对数据元素执行处理操作。指令解码器响应于至少一个但不超过N个重排指令，其中N是奇数复数，以产生控制信号，以控制处理电路执行至少等同于：作为源数据元素的重新排列过程存储在由所述至少一个重新布置指令识别的所述寄存器数据存储器的N个寄存器中的数据元素; 执行重排操作以在常规N路交错顺序和解交织顺序之间重新排列源数据元素，以便产生结果数据元素的序列; 并输出用于存储在寄存器数据存储器中的结果数据元素的序列。这提供了一种特别有效的技术，用于执行N路交错和解交织操作，其中N是奇数，导致高性能，低能量消耗和降低的寄存器使用，与已知的现有技术相比。

6. 发明授权

US08595280B2 Apparatus and method for performing multiply-accumulate operations 有权
标题翻译：用于执行多重累加操作的装置和方法
公开(公告)号：US08595280B2
公开(公告)日：2013-11-26
申请号：US12926171
申请日：2010-10-29
申请人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
发明人： Dominic Hugo Symes , Mladen Wilder , Guy Larri
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.
摘要翻译：提供了一种用于执行多重累加操作的数据处理装置和方法。数据处理装置包括响应于控制信号的数据处理电路，以对至少一个输入数据元素执行数据处理操作。指令解码器电路响应于指定作为输入操作数的第一输入数据元素，第二输入数据元素和谓词值的预测乘法累加指令，以产生控制信号以控制数据处理电路执行乘法累加操作通过：将所述第一输入数据元素和所述第二输入数据元素相乘以产生乘法数据元素; 如果谓词值具有第一值，则通过将乘数据元素添加到初始累加数据元素来产生结果累积数据元素; 并且如果谓词值具有第二值，则通过从初始累加数据元素中减去乘法数据元素来产生结果累积数据元素。这种方法提供了一种特别有效的机制，用于执行乘法和乘法运算的复杂序列，与已知的现有技术相比，有助于提高性能，能量消耗和代码密度。

7. 发明授权

US08255446B2 Apparatus and method for performing rearrangement and arithmetic operations on data 有权
标题翻译：对数据执行重排和算术运算的装置和方法
公开(公告)号：US08255446B2
公开(公告)日：2012-08-28
申请号：US11987323
申请日：2007-11-29
申请人： Daniel Kershaw , Mladen Wilder , Dominic Hugo Symes
发明人： Daniel Kershaw , Mladen Wilder , Dominic Hugo Symes
IPC分类号： G06F7/38
CPC分类号： G06F7/768 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing Single Instruction Multiple Data (SIMD) processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation. The associated method involves controlling processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation in response to a combined rearrangement arithmetic instruction and providing the scalar logic size parameter to configure the rearrangement operation. A computer program product is also provided comprising at least one combined rearrangement arithmetic instruction.
摘要翻译：提供了一种用于对数据执行重新排列操作和算术运算的装置和方法。数据处理装置具有用于执行单指令多数据（SIMD）处理操作和标量处理操作的处理电路，响应于程序指令来存储数据和控制电路的寄存器组，以控制处理电路执行数据处理操作。控制电路被布置为响应于组合重排算术指令来控制处理电路对存储在寄存器组中的多个数据元素执行重新排列操作和至少一个SIMD算术运算。重新布置操作可以由至少部分地从寄存器库导出的尺寸参数来配置。尺寸参数提供形成用于重排操作的重新排列元件的数量元素的数量的指示。相关联的方法涉及控制处理电路以响应于组合重排算术指令执行重排操作和至少一个SIMD算术运算，并提供标量逻辑大小参数以配置重新排列操作。还提供了包括至少一个组合重排算术指令的计算机程序产品。

8. 发明申请

US20120133533A1 Storage of probability values for contexts used in arithmetic coding 有权
标题翻译：存储算术编码中使用的上下文的概率值
公开(公告)号：US20120133533A1
公开(公告)日：2012-05-31
申请号：US12926601
申请日：2010-11-29
申请人： Anders Berkeman , Dominic Hugo Symes
发明人： Anders Berkeman , Dominic Hugo Symes
IPC分类号： H03M7/00
CPC分类号： H03M7/4018
摘要： Arithmetic coding utilises probability values associated with contexts and context indexed values. The probability values are stored within a random access memory 6 from where they are fetched to a cache memory 8 before being supplied to an arithmetic encoder and decoder 4. The context indexed values used are mapped to the plurality of contexts employed such that context indexed values used to process data values close by in a position within the stream of data values being processed have a greater statistical likelihood of sharing a group of contexts than context values used to process data values far away in position within the stream of data values. Thus, a group of contexts for which the probability values are fetched together into the cache memory 8 will have an increased statistical likelihood of being used together in close proximity in processing the stream of data values. This reduces the number of cache flush operations and cache line fill operations.
摘要翻译：算术编码利用与上下文和上下文索引值相关联的概率值。概率值被存储在随机存取存储器6中，从它们被提取到高速缓冲存储器8之前被提供给算术编码器和解码器4.所使用的上下文索引值被映射到所使用的多个上下文，使得上下文索引值用于处理在被处理的数据值的流中的位置附近的数据值具有与用于处理在数据值流内远离位置的数据值的上下文值共享一组上下文的更大的统计学可能性。因此，将概率值一起提取到高速缓存存储器8中的一组上下文将具有在处理数据值流时紧密一起使用的增加的统计似然性。这减少了高速缓存刷新操作和高速缓存行填充操作的数量。

9. 发明申请

US20090187746A1 Apparatus and method for performing permutation operations on data 有权
标题翻译：用于对数据执行置换操作的装置和方法
公开(公告)号：US20090187746A1
公开(公告)日：2009-07-23
申请号：US12314760
申请日：2008-12-16
申请人： Dominic Hugo Symes , Mladen Wilder
发明人： Dominic Hugo Symes , Mladen Wilder
IPC分类号： G06F9/302
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036
摘要： An apparatus for processing data is provided comprising processing circuitry having permutation circuitry for performing permutation operations, a register bank having a plurality of registers for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to be responsive to a control-generating instruction to generate in dependence upon a bit-mask control signals to configure permutation circuitry for performing permutation operation on an input operand. The bit-mask identifies within the input operand the first group of data elements having a first ordering and a second group of data elements having a second ordering and the permutation operation is such that it preserves one of the first ordering and the second ordering but changes the other of the first ordering and the second ordering.
摘要翻译：提供了一种用于处理数据的装置，其包括具有用于执行置换操作的置换电路的处理电路，具有用于存储数据的多个寄存器的寄存器组和响应于程序指令控制处理电路执行数据处理操作的控制电路。控制电路被布置为响应于控制生成指令，以根据位掩码控制信号来产生以配置用于对输入操作数执行置换操作的置换电路。位掩码在输入操作数内识别具有第一排序的第一组数据元素和具有第二排序的第二组数据元素，并且置换操作使得其保留第一排序和第二排序之一，但是改变第一个订购中的另一个和第二个订购。

10. 发明授权

US07315875B2 Data filtering 有权
标题翻译：数据过滤
公开(公告)号：US07315875B2
公开(公告)日：2008-01-01
申请号：US10764473
申请日：2004-01-27
申请人： Paul Matthew Carpenter , Dominic Hugo Symes
发明人： Paul Matthew Carpenter , Dominic Hugo Symes
IPC分类号： G06F17/10
CPC分类号： H04N19/86 , H04N19/42 , H04N19/61
摘要： A method, computer program product and data processing apparatus for filtering data, in particular for use in deblocking filters. The method comprising applying a plurality of m filter coefficients which each have a value which is a negative power of two and which sum to one, to a plurality of m input data items to produce a filtered output data item, by performing a sequence of averaging calculations comprising averaging input data items to which a smallest filter coefficient is to be applied to produce first averaged data and averaging the first averaged data with other averaged input data or with input data items to which larger filter coefficients are to be applied the plurality of m filter coefficients being applied to the plurality of m input data items via a sequence of averaging calculations such that a data width of any calculated data does not exceed that of the input data being averaged.
摘要翻译：一种用于过滤数据的方法，计算机程序产品和数据处理装置，特别是用于去块滤波器。该方法包括：将多个m个滤波器系数应用于多个m个滤波器系数，该多个m个滤波器系数中的每一个均具有为2的负值并且与1相加的值，并通过执行平均序列来施加到多个m个输入数据项以产生滤波后的输出数据项计算包括对要应用最小滤波器系数的输入数据项进行平均以产生第一平均数据，并且对其他平均输入数据进行平均化，或者与要对其应用更大滤波器系数的输入数据项进行平均滤波器系数经由平均计算序列被施加到多个m个输入数据项，使得任何计算数据的数据宽度不超过正被平均的输入数据的数据宽度。

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