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1. 发明专利

JP2011166111A Method of manufacturing layered chip package 有权
标题翻译：制造分层芯片包装的方法
公开(公告)号：JP2011166111A
公开(公告)日：2011-08-25
申请号：JP2010225899
申请日：2010-10-05
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , IIJIMA ATSUSHI
IPC分类号： H01L25/065 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L24/96 , H01L21/6836 , H01L23/3178 , H01L23/544 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L2224/24101 , H01L2224/24105 , H01L2224/24137 , H01L2224/24147 , H01L2224/25175 , H01L2224/2929 , H01L2224/32145 , H01L2224/73267 , H01L2224/821 , H01L2224/8385 , H01L2224/94 , H01L2224/96 , H01L2924/07802 , Y10S438/928 , H01L2924/00014 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To mass-produce layered chip packages at low cost in a short time. SOLUTION: In a method of manufacturing a layered laminated chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages, where the layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces 109a, 109b. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces 109a facing each other, and then the second surface 109b of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface 109b of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在短时间内以低成本批量生产分层芯片封装。解决方案：在层叠层叠芯片封装的制造方法中，制造层叠子结构，并用于制造多层分层芯片封装，其中分层子结构包括堆叠的第一至第四子结构，每个子结构包括阵列的多个预备层部分。在制造层状子结构的步骤中，最初制造的是具有第一和第二表面109a，109b的第一至第四预抛光子结构。接下来，第一和第二预抛光子结构彼此接合，第一表面109a彼此面对，然后抛光第二预抛光子结构的第二表面109b以形成第一叠层。类似地，第三和第四预抛光子结构彼此结合，并且抛光第三预抛光子结构的第二表面109b以形成第二堆叠。然后，第一和第二堆叠彼此结合。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2011166110A Method of manufacturing layered chip package 有权
标题翻译：制造分层芯片包装的方法
公开(公告)号：JP2011166110A
公开(公告)日：2011-08-25
申请号：JP2010225898
申请日：2010-10-05
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , IIJIMA ATSUSHI
IPC分类号： H01L25/10 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/11 , H01L25/18
CPC分类号： H01L24/05 , H01L21/76898 , H01L24/03 , H01L24/24 , H01L24/25 , H01L24/32 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/05599 , H01L2224/20 , H01L2224/211 , H01L2224/94 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2224/83 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To mass-produce layered chip packages with wiring formed on the side surfaces of the respective main bodies at low cost in a short time, and to form the wiring with precision. SOLUTION: The layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each of the plurality of structures includes at least one main-body-forming portion including a pre-wiring surface 2Pc. Next, the plurality of structures are surrounded for alignment with a jig 122 including an upper surface positioned lower than the pre-wiring surface 2Pc so that the pre-wiring surfaces 2Pc face upward. Next, a resin layer 133 covering the jig 122 and the plurality of structures is formed using a resin film. Next, the resin layer 133 is polished until the pre-wiring surfaces 2Pc are exposed. Next, the wiring is formed collectively on the pre-wiring surfaces 2Pc. Then, the main-body-forming portions are separated. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在短时间内以低成本批量生产在各主体的侧表面上形成的布线的分层芯片封装，并且精确地形成布线。解决方案：分层芯片封装包括主体和布置在主体的侧表面上的布线。主体包括多个层部分。在制造层状芯片封装的方法中，最初形成多个结构。多个结构中的每一个包括至少一个包括预布线表面2Pc的主体形成部分。接下来，多个结构被包围以与包括位于比预布线表面2Pc低的上表面的夹具122对准，使得预布线表面2Pc面向上。接下来，使用树脂膜形成覆盖夹具122的树脂层133和多个结构体。接下来，抛光树脂层133直到预接线表面2Pc露出。接下来，将布线集中地形成在预接线表面2Pc上。然后，分离主体成形部。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011097008A Method of manufacturing layered chip package 有权
标题翻译：制造分层芯片包装的方法
公开(公告)号：JP2011097008A
公开(公告)日：2011-05-12
申请号：JP2010109888
申请日：2010-05-12
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , IKEJIMA HIROSHI , IIJIMA ATSUSHI
IPC分类号： H01L25/065 , H01L21/3205 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L24/03 , H01L21/76898 , H01L24/05 , H01L24/24 , H01L24/25 , H01L24/32 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/05541 , H01L2224/0555 , H01L2224/0556 , H01L2224/05599 , H01L2224/20 , H01L2224/94 , H01L2225/06551 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2224/83 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To mass-produce a layered chip package at low cost in a short time. SOLUTION: The layered chip package includes a body, and wiring disposed on at least one side surface of the body. The body has: a main part having an upper surface and a lower surface and including a plurality of layer portions stacked; and a plurality of terminals arranged on at least one of the upper and the lower surfaces of the main part and electrically connected to the wiring. A method of manufacturing the layered chip package includes: fabricating a plurality of first layered base substructures each including a plurality of pre-separation main bodies 2P arrayed; fabricating a second layered base substructure by stacking the plurality of first layered substructures; cutting the second layered base substructure into a block 121 in which a plurality of pre-separation main bodies 2P are arrayed in two directions; forming the wiring simultaneously for the plurality of pre-separation main bodies 2P included in the block 121; and separating the plurality of pre-separation main bodies from each other. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在短时间内以低成本批量生产分层芯片封装。解决方案：层状芯片封装包括主体和布置在主体的至少一个侧表面上的布线。本体具有：具有上表面和下表面的主要部分，并且包括堆叠的多个层部分; 以及多个端子，其布置在主要部件的上表面和下表面中的至少一个上并电连接到布线。制造层状芯片封装的方法包括：制造多个第一分层基底子结构，每个第一分层基底子结构包括排列的多个预分离主体2P; 通过堆叠多个第一分层子结构制造第二分层基底子结构; 将第二分层基底子结构切割成其中多个预分离主体2P沿两个方向排列的块121; 为包括在块121中的多个预分离主体2P同时形成布线; 以及将所述多个预分离主体彼此分离。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011044221A Method of manufacturing magnetic head for perpendicular magnetic recording including two side shields 有权
标题翻译：制造包括双面胶片在内的磁性记录磁头的方法
公开(公告)号：JP2011044221A
公开(公告)日：2011-03-03
申请号：JP2010054501
申请日：2010-03-11
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ISHIZAKI KAZUO , ARAKI HIRONORI , ITO HIROYUKI , TANEMURA SHIGEKI , IIJIMA ATSUSHI
IPC分类号： G11B5/31
CPC分类号： G11B5/3116 , G11B5/1278 , G11B5/3163 , G11B5/3967 , Y10T29/49039 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052
摘要： PROBLEM TO BE SOLVED: To attain an accurate alignment of a pole layer and two side shields with respect to each other, a control of respective shapes of the pole layer and two side shields, and a reduction in the distance between the pole layer and each of the two side shields. SOLUTION: The magnetic head includes: the pole layer 12; two side shields 13C1, 13C2; and an encasing layer 25 having a pole groove 25a that accommodates the pole layer and the two side shields, and first and second side shield grooves 25b1, 25b2. In the method of manufacturing the magnetic head, the pole groove and first and second initial side shield grooves are formed in a nonmagnetic layer using an etching mask layer having first to third openings, and wall faces of first and second initial side shield grooves that are closer to the pole groove are etched by a dry etching to thereby complete the first and second side shield grooves 25b1, 25b2. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题为了获得相对于彼此的极性层和两个侧面屏蔽件的精确对准，控制极性层和两个侧面屏蔽件的各个形状以及极点之间的距离的减小层和两个侧面屏蔽中的每一个。解决方案：磁头包括：极层12; 两个侧屏13C1，13C2; 以及具有容纳极性层和两个侧面屏蔽的极槽25a以及第一和第二侧面屏蔽槽25b1,25b2的封装层25。在制造磁头的方法中，使用具有第一至第三开口的蚀刻掩模层将第一和第二初始侧屏蔽槽形成为非磁性层，第一和第二初始侧屏蔽槽的壁面为通过干蚀刻蚀刻更靠近极槽的凹槽，从而完成第一和第二侧屏蔽槽25b1,25b2。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2010050453A Laminated chip package and method of manufacturing the same 有权
标题翻译：层压芯片包装及其制造方法
公开(公告)号：JP2010050453A
公开(公告)日：2010-03-04
申请号：JP2009185554
申请日：2009-08-10
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU , IKEJIMA HIROSHI
IPC分类号： H01L25/065 , H01L21/3205 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enable use of a chip not normally operated, while reducing the problem resulting from wiring connected to the chip which does not work normally. SOLUTION: A laminated chip package 1 includes a body 2, having a plurality of laminated layers 11-18 and wiring 3A, 3B provided on the side surfaces of the body 2. The plurality of layers include a first type of layers 11-16 and 18 and a second type of layer 17. Each of the first and second types of layers includes a semiconductor chip. The first type of layers are connected to the respective semiconductor chips and include a plurality of electrodes, having end faces provided on the side surfaces of the body 2 and provided with the wirings 3A, 3B thereon. The second type of layer, meanwhile, is connected to the associated semiconductor chip but does not include an electrode having its end face provided on the side surface of the body 2 and provided with the wirings 3A, 3B thereon. The wirings 3A, 3B are connected to the end faces of the plurality of electrodes. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了使得能够使用不正常操作的芯片，同时减少由于连接到不能正常工作的芯片的布线引起的问题。解决方案：层叠芯片封装1包括主体2，其具有设置在主体2的侧表面上的多个层叠层11-18和布线3A，3B。多个层包括第一类型的层11 -16和18以及第二类型的层17.第一和第二类型层中的每一个包括半导体芯片。第一类型的层连接到相应的半导体芯片，并且包括多个电极，其端面设置在主体2的侧表面上并且在其上设置有布线3A，3B。同时，第二类型的层连接到相关联的半导体芯片，但不包括其端面设置在主体2的侧表面上并且在其上设置有布线3A，3B的电极。配线3A，3B与多个电极的端面连接。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009295262A Thin-film magnetic head, method of manufacturing the same, head gimbal assembly, and hard disk drive 有权
标题翻译：薄膜磁头，其制造方法，头部组件和硬盘驱动
公开(公告)号：JP2009295262A
公开(公告)日：2009-12-17
申请号：JP2009112227
申请日：2009-05-01
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , IIJIMA ATSUSHI
IPC分类号： G11B5/31
CPC分类号： G11B5/3116 , G11B5/1278 , G11B5/3163
摘要： PROBLEM TO BE SOLVED: To shorten a magnetic path length while securing the number of necessary turns, and to suppress the protrusion of a write shield layer in a thin-film magnetic head for performing a magnetic recording operation, by a perpendicular magnetic recording system, a method for manufacturing the same, a head gimbal assembly, and a hard disk drive. SOLUTION: The thin-film magnetic head 300 is constructed such that a main magnetic pole layer having a magnetic pole end on a side of ABS opposing a recording medium, a write shield layer opposing the main magnetic pole layer on the ABS side, a gap layer formed between the main magnetic pole layer and the write shield layer, and a thin-film coil wound about the write shield layer or the main magnetic pole layer are laminated on a substrate. This thin-film magnetic head has an equidistant two-stage structure in which a first turn part of a first conductor layer and a second turn part of a second conductor layer overlap vertically along the ABS, and which has the same front distance from respective front side faces closer to the ABS. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了缩短磁路长度，同时确保必要的匝数，并且通过垂直磁场抑制用于执行磁记录操作的薄膜磁头中的写入屏蔽层的突出记录系统，其制造方法，头万向架组件和硬盘驱动器。解决方案：薄膜磁头300被构造成使得在ABS侧的磁极端与记录介质相对的主磁极层，与ABS侧上的主磁极层相对的写入屏蔽层在主磁极层和写入屏蔽层之间形成的间隙层和缠绕在写入屏蔽层或主磁极层上的薄膜线圈层叠在基板上。这种薄膜磁头具有等距离的两级结构，其中第一导体层的第一匝部分和第二导体层的第二匝部分沿着ABS垂直重叠，并且具有与前面相同的前部距离侧面靠近ABS。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2009151917A Thin film magnetic head 有权
标题翻译：薄膜磁头
公开(公告)号：JP2009151917A
公开(公告)日：2009-07-09
申请号：JP2008220311
申请日：2008-08-28
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , KAMIKAMA TAKEHIRO , ARAKI HIRONORI
IPC分类号： G11B5/31 , G11B5/127 , G11B5/187 , H04R31/00
CPC分类号： G11B5/1877 , G11B5/31 , Y10T29/49032 , Y10T29/49039 , Y10T29/49044 , Y10T29/49046 , Y10T29/49052
摘要： PROBLEM TO BE SOLVED: To provide a thin film magnetic head capable of easily making write track width narrower. SOLUTION: The thin film magnetic head 40 has a structure wherein a first magnetic pole layer 10, a second magnetic pole layer 26, a recording gap layer 25 and a thin film coil 116 are layered. The first (lower) magnetic pole layer 10 and the second (upper) magnetic pole layer 26 are magnetically connected and have a fourth lower magnetic pole part 10d and a first upper magnetic pole part 26a, respectively. The thin film coil 116 has a first conduction part 112 and a second conduction part 111, the second conduction part 111 is disposed between the lower magnetic pole layer 10 and the first conduction part 112 and the lower magnetic pole layer 10 and the first conduction part 112 come in contact with the second conduction part 111 via an insulating film 15 for separation. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够容易地使写入轨道宽度变窄的薄膜磁头。解决方案：薄膜磁头40具有层叠第一磁极层10，第二磁极层26，记录间隙层25和薄膜线圈116的结构。第一（下）磁极层10和第二（上）磁极层26磁性连接，并且分别具有第四下磁极部10d和第一上磁极部26a。薄膜线圈116具有第一导电部分112和第二导电部分111，第二导电部分111设置在下磁极层10和第一导电部分112之间，下磁极层10和第一导电部分 112经由用于分离的绝缘膜15与第二导电部111接触。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2012009807A Layered chip package and method of manufacturing same 有权
标题翻译：层状芯片包装及其制造方法
公开(公告)号：JP2012009807A
公开(公告)日：2012-01-12
申请号：JP2010288172
申请日：2010-12-24
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , IKEJIMA HIROSHI , IIJIMA ATSUSHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/76898 , H01L23/522 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02317 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05554 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/83121 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/85 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2221/68304
摘要： PROBLEM TO BE SOLVED: To provide a layered chip package that facilitates implementing a package that provides, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included.SOLUTION: A layered chip package 1A, 1B includes a main body 2, and wiring 3 disposed on a side surface of the main body 2. The main body 2 includes: a main part 2M including a plurality of layer portions; a plurality of first terminals 4 disposed on the top surface of the main part 2M and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part 2M and connected to the wiring. The plurality of layer portions include a first-type layer portion 10A and a second-type layer portion 10B. The first-type layer portion 10A includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion 10B includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.
摘要翻译：要解决的问题：为了提供便于实现包括即使包括故障半导体芯片的封装的分层芯片封装，其功能与不包括故障半导体芯片的功能相同。解决方案：层叠芯片封装1A，1B包括主体2和布置在主体2的侧表面上的布线3.主体2包括：包括多个层部分的主体部分2M; 多个第一端子4，其设置在主体部件2M的上表面上，与该布线连接; 以及多个第二端子，其设置在主体部件2M的底面上，与该布线连接。多个层部分包括第一类型部分10A和第二类型部分10B。第一类型部分10A包括符合标准的半导体芯片和连接到半导体芯片和布线的多个第一类型的电极。第二类型部分10B包括有缺陷的半导体芯片和多个第二类型的电极，其连接到布线而不连接到半导体芯片。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011166109A Method of manufacturing layered chip package 有权
标题翻译：制造分层芯片包装的方法
公开(公告)号：JP2011166109A
公开(公告)日：2011-08-25
申请号：JP2010215273
申请日：2010-09-27
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , IIJIMA ATSUSHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/78 , H01L2224/16
摘要： PROBLEM TO BE SOLVED: To mass-produce layered chip packages at low cost in a short time. SOLUTION: The layered chip package includes: a main body including a plurality of layer portions stacked; and wiring disposed on at least one side surface of the main body. In a method of manufacturing the layered chip package, first, a plurality of substructures each of which including an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies 2P arranged in rows. Next, the layered substructure is cut into a plurality of blocks 116 each of which includes a row of a plurality of pre-separation main bodies 2P, and the wiring is collectively formed on the plurality of pre-separation main bodies 2P included in each block 116. The plurality of pre-separation main bodies 2P are then separated from each other. Each of the plurality of blocks 116 includes a row of three, four, or five pre-separation main bodies 2P. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在短时间内以低成本批量生产分层芯片封装。解决方案：层状芯片封装包括：主体，其包括堆叠的多个层部分; 以及布置在主体的至少一个侧表面上的布线。在制造层状芯片封装的方法中，首先，使用包括多个预备层部分的阵列的多个子结构来制造层叠子结构，其包括排列成行的多个预分离主体2P 。接下来，将分层子结构切割成多个块116，每个块116包括一排多个预分离主体2P，并且布线集中地形成在包括在每个块中的多个预分离主体2P上然后，将多个预分离主体2P彼此分离。多个块116中的每一个包括一行三个，四个或五个预分离主体2P。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2010232705A Manufacturing method of electronic component package 有权
标题翻译：电子元件封装的制造方法
公开(公告)号：JP2010232705A
公开(公告)日：2010-10-14
申请号：JP2010164827
申请日：2010-07-22
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , SHIMIZU TATSUJI
IPC分类号： H01L25/00
CPC分类号： H01L23/49805 , H01L23/49548 , H01L23/49575 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0655 , H01L25/50 , H01L2224/04105 , H01L2224/24137 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To mass produce an electronic component package with a low cost in a short period of time. SOLUTION: A manufacturing method for an electronic component package forms at first a wafer 1 which includes: a plurality of sets of an external connection terminals 11 corresponding to a plurality of electronic component packages; a holding part 15 for holding the plurality of sets of the external connection terminals 11; and a plurality of a substrate scheduled parts 2 that form a substrate of the electronic component package and respectively later by being mutually separated. Then, at least one electronic component chip 3 is joined to each substrate scheduled part 2 in the wafer 1; an electrode of the electronic component chip 3 and the external connection terminal 11 are connected; the electronic component chip 3 are sealed; and the wafer 1 is cut such that the respective substrate scheduled parts 2 are separated from each other to form a plurality of the substrates. The plurality of the external connection terminals are exposed on the side surfaces of the substrate. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在短时间内大量生产具有低成本的电子部件封装。解决方案：电子部件封装的制造方法首先形成晶片1，晶片1包括：对应于多个电子部件封装的多组外部连接端子11; 用于保持多组外部连接端子11的保持部15; 以及分别形成电子部件封装的基板的多个基板调度部2，其后分别相互分离。然后，将至少一个电子元件芯片3接合到晶片1中的每个基板调度部分2; 连接电子元件芯片3的电极和外部连接端子11; 电子部件芯片3被密封; 并且切割晶片1使得各个基板调度部分2彼此分离以形成多个基板。多个外部连接端子露出在基板的侧表面上。版权所有（C）2011，JPO＆INPIT

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