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1. 发明专利

JP2010109333A Layered chip package with heat sink 有权
标题翻译：散热片包装与散热
公开(公告)号：JP2010109333A
公开(公告)日：2010-05-13
申请号：JP2009207678
申请日：2009-09-09
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU , IKEJIMA HIROSHI
IPC分类号： H01L23/36 , H01L23/473 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/367 , H01L23/427 , H01L25/50 , H01L2224/24145 , H01L2225/0651 , H01L2225/06551 , H01L2225/06589
摘要： PROBLEM TO BE SOLVED: To increase a heat dissipation effect of a heat sink without an increase in size in a layered chip package that includes a plurality of chips stacked and a heat sink. SOLUTION: The layered chip package 1 includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink 70, 80. Each of the plurality of layer portions has a top surface, a bottom surface and four side surfaces. The heat sink 70, 80 has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在包括堆叠的多个芯片和散热器的分层芯片封装中，增加散热器的散热效果而不增加尺寸。解决方案：层状芯片封装1包括：堆叠多个层部分，每个层部分包括半导体芯片; 和散热片70,80。多个层部分中的每一个具有顶表面，底表面和四个侧表面。散热器70,80具有至少一个第一部分和耦合到该至少一个第一部分的第二部分。所述至少一个第一部分邻近所述层部分中的至少一个的顶表面或底表面。第二部分与多个层部分中的至少两个层部分中的每一个的一个侧表面相邻。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010050453A Laminated chip package and method of manufacturing the same 有权
标题翻译：层压芯片包装及其制造方法
公开(公告)号：JP2010050453A
公开(公告)日：2010-03-04
申请号：JP2009185554
申请日：2009-08-10
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU , IKEJIMA HIROSHI
IPC分类号： H01L25/065 , H01L21/3205 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enable use of a chip not normally operated, while reducing the problem resulting from wiring connected to the chip which does not work normally. SOLUTION: A laminated chip package 1 includes a body 2, having a plurality of laminated layers 11-18 and wiring 3A, 3B provided on the side surfaces of the body 2. The plurality of layers include a first type of layers 11-16 and 18 and a second type of layer 17. Each of the first and second types of layers includes a semiconductor chip. The first type of layers are connected to the respective semiconductor chips and include a plurality of electrodes, having end faces provided on the side surfaces of the body 2 and provided with the wirings 3A, 3B thereon. The second type of layer, meanwhile, is connected to the associated semiconductor chip but does not include an electrode having its end face provided on the side surface of the body 2 and provided with the wirings 3A, 3B thereon. The wirings 3A, 3B are connected to the end faces of the plurality of electrodes. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了使得能够使用不正常操作的芯片，同时减少由于连接到不能正常工作的芯片的布线引起的问题。解决方案：层叠芯片封装1包括主体2，其具有设置在主体2的侧表面上的多个层叠层11-18和布线3A，3B。多个层包括第一类型的层11 -16和18以及第二类型的层17.第一和第二类型层中的每一个包括半导体芯片。第一类型的层连接到相应的半导体芯片，并且包括多个电极，其端面设置在主体2的侧表面上并且在其上设置有布线3A，3B。同时，第二类型的层连接到相关联的半导体芯片，但不包括其端面设置在主体2的侧表面上并且在其上设置有布线3A，3B的电极。配线3A，3B与多个电极的端面连接。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010183058A Layered chip package and method of manufacturing the same 有权
标题翻译：层状芯片包装及其制造方法
公开(公告)号：JP2010183058A
公开(公告)日：2010-08-19
申请号：JP2009207679
申请日：2009-09-09
申请人： Headway Technologies Inc , Sae Magnetics (Hk) Ltd , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU , IKEJIMA HIROSHI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/82 , H01L24/94 , H01L24/96 , H01L25/50 , H01L2221/68359 , H01L2223/54426 , H01L2224/05554 , H01L2224/18 , H01L2224/48 , H01L2224/48463 , H01L2224/49175 , H01L2224/4943 , H01L2224/94 , H01L2225/06551 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/03
摘要： PROBLEM TO BE SOLVED: To disable a chip that does not operate normally while reducing a problem resulting from a wire connected to the chip that does not operate normally. SOLUTION: A layered chip package 1 comprises a body 2 including a plurality of pairs of layer portions and wires 3A and 3B arranged on the side surfaces of the body 2. The plurality of pairs of layer portions includes a specific pair of layer portions 10PS having a first type layer portion and a second type layer portion. The first-type layer portion is connected to a semiconductor chip and includes a plurality of electrodes having an end surface arranged on the side surface of the body 2 but the second type of layer portion does not. A laminated body in which two or more pairs of layer portions, the number of which is determined in advance, are stacked is manufactured using a laminated foundation structure in which two foundation structures including a plurality of arranged spare layer portions are stacked and the body 2 is manufactured by stacking the first type layer portions to be added in the same number as that of the specific pairs of layer portions included therein. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：禁用不能正常工作的芯片，同时减少连接到芯片的导线不能正常工作的问题。解决方案：分层芯片封装1包括主体2，主体2包括多对层部分和布置在主体2的侧表面上的导线3A和3B。多对层部分包括特定的一对层部分10PS具有第一类型层部分和第二类型部分。第一型层部连接到半导体芯片，并且包括多个电极，其具有布置在主体2的侧表面上的端面，但第二类型层部分不具有端面。使用层叠基层结构制造其中预先确定了数个层数的两层或多层的层叠体，其中堆叠了两个包括多个布置的备用层部分的基础结构，并且主体2 通过堆叠要添加的第一类型的层部分与其中包括的特定的层部分对相同的数量来制造。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010016374A Layered chip package, and method of manufacturing the same 有权
标题翻译：层状芯片封装及其制造方法
公开(公告)号：JP2010016374A
公开(公告)日：2010-01-21
申请号：JP2009148254
申请日：2009-06-23
申请人： Headway Technologies Inc , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/544 , H01L21/6835 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2224/48463 , H01L2224/4943 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To mass-produce layered chip packages inexpensively in a short time. SOLUTION: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures 110 each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face each other; and forming a first and a second substructure 110 by polishing the second surfaces. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在短时间内廉价地批量生产分层芯片封装。解决方案：层叠芯片封装包括堆叠的多个层部分，每个层部分包括具有形成在其上的器件的第一表面和与其相对的第二表面的半导体芯片。多个层部分包括至少一对层部分，这些层部分设置成使得各个半导体芯片的第一表面彼此面对。层叠芯片封装的制造方法包括以下步骤：通过堆叠多个子结构110来制造分层子结构，每个子结构110包括对应于层状芯片封装的多个层部分的多个层部分; 以及通过使用层状子结构制造多个分层芯片封装。制造层状子结构的步骤包括：制造每个具有第一表面和第二表面的第一和第二预抛光子结构; 将预抛光子结构彼此粘合，使得它们各自的第一表面彼此面对; 以及通过抛光所述第二表面来形成第一和第二子结构110。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2013150010A Method for manufacturing laminated chip package 有权
标题翻译：制造层压芯片包装的方法
公开(公告)号：JP2013150010A
公开(公告)日：2013-08-01
申请号：JP2013089040
申请日：2013-04-22
申请人： Headway Technologies Inc , ヘッドウェイテクノロジーズインコーポレイテッド , Tdk Corp , Tdk株式会社
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU
IPC分类号： H01L25/065 , H01L21/304 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L23/544 , H01L21/6835 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2224/48463 , H01L2224/4943 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To enable mass production of a laminated chip package at low costs and in a short time.SOLUTION: A laminated chip package comprises a plurality of laminated layer portions each including a semiconductor chip having a first surface having a device formed thereon and a second surface on a side opposite to the first surface. The plurality of layer portions includes one pair or more of layer portions arranged so that the first surface of the semiconductor chip faces each other. A method for manufacturing the laminated chip package comprises: laminating a plurality of substructures 110 including a plurality of layer portions each corresponding to each of the plurality of layer portions of the laminated chip package to form a laminated substructure; and forming the plurality of laminated chip packages by using the laminated substructure. In the step of forming the laminated substructure, first and second pre-polishing substructures each having first and second surfaces are formed, and the substructures are bonded so that the first surface faces each other, and the second surfaces are polished to form first and second substructures 110.
摘要翻译：要解决的问题：能够以低成本和短时间大量生产层压芯片封装。解决方案：层叠芯片封装包括多个层叠层部分，每个层叠层部分包括具有形成在其上的器件的第一表面的半导体芯片以及与第一表面相对的一侧上的第二表面。多个层部分包括一对或多个层部分，其布置成使得半导体芯片的第一表面彼此面对。一种层叠芯片封装的制造方法，其特征在于，层叠多个子结构110，所述多个子结构110包括多个层状部，各层对应于层叠芯片封装的多个层部，以及通过使用层压子结构形成多个层压芯片封装。在形成层叠子结构的步骤中，形成具有第一表面和第二表面的第一和第二预抛光子结构，并且将子结构粘合，使得第一表面彼此面对，并且将第二表面抛光以形成第一和第二表面子结构110。

6. 发明专利

JP2010087502A Layered chip package for implementing memory device 有权
标题翻译：用于实施存储器件的层叠芯片包
公开(公告)号：JP2010087502A
公开(公告)日：2010-04-15
申请号：JP2009207677
申请日：2009-09-09
申请人： Headway Technologies Inc , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU , HASHIMOTO RYUJI
IPC分类号： H01L25/065 , H01L21/3205 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/6835 , H01L23/544 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/94 , H01L24/96 , H01L25/105 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/16 , H01L2224/18 , H01L2224/48091 , H01L2224/48464 , H01L2224/49175 , H01L2224/4943 , H01L2225/06513 , H01L2225/06524 , H01L2225/06551 , H01L2225/1011 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a layered chip package for implementing a memory device, which can easily form wiring for electrical connections among chips and can improve wiring reliability. SOLUTION: The layered chip package 1 includes a body 2, and wiring leads 3A, 3B disposed on a side face of the body 2. The body 2 includes: many first-type layer portions 12 to 18 each including a first-type semiconductor chip; and a second-type layer portion 11 including a second-type semiconductor chip. The first-type semiconductor chip includes many memory cells. The second-type semiconductor chip includes a control circuit that controls writing and reading to and from the memory cells included in many first-type layer portions. Each layer portion includes an insulating portion covering at least one side surface of the semiconductor chip, and many electrodes connected to the semiconductor chip. Each of the electrodes has an end face that is located at the side surface of the body 2 and connected to the wiring leads 3A, 3B. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于实现存储器件的分层芯片封装，其可以容易地形成用于芯片之间的电连接的布线，并且可以提高布线可靠性。解决方案：层叠芯片封装1包括主体2和布置在主体2的侧面上的布线引线3A，3B。主体2包括：许多第一型层部分12至18，型半导体芯片; 以及包括第二类型半导体芯片的第二类型层部分11。第一型半导体芯片包括许多存储单元。第二种类型的半导体芯片包括一个控制电路，该控制电路控制许多第一类型层部分中包含的存储单元的写入和读出。每层部分包括覆盖半导体芯片的至少一个侧表面的绝缘部分和连接到半导体芯片的许多电极。每个电极具有位于主体2的侧表面并连接到布线引线3A，3B的端面。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010016375A Layered chip package, and method of manufacturing the same 有权
标题翻译：层状芯片封装及其制造方法
公开(公告)号：JP2010016375A
公开(公告)日：2010-01-21
申请号：JP2009148255
申请日：2009-06-23
申请人： Headway Technologies Inc , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/6835 , H01L23/544 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/95 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/07802 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To mass-produce layered chip packages inexpensively in a short time, and to diversify electric connections between a plurality of layered chip packages. SOLUTION: A layered chip package 1 includes: a body 2 including a plurality of layer portions 11 to 18; wiring portions 3A and 3B disposed on a side surface of the body 2; a plurality of first terminals 22A disposed on a top surface of the body 2; and a plurality of second terminals 22B disposed on a bottom surface of the body 2. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the body 2 on which the wiring portions 3A and 3B are disposed. The wiring portions 3A and 3B are connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals 22A and 22B. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了在短时间内廉价地批量生产分层芯片封装，并且使多个层叠芯片封装之间的电连接多样化。解决方案：层状芯片封装1包括：主体2，其包括多个层部分11至18; 布置在主体2的侧表面上的布线部分3A和3B; 设置在主体2的上表面上的多个第一端子22A; 以及设置在主体2的底表面上的多个第二端子22B。每个层部分包括半导体芯片，覆盖半导体芯片的至少一个侧表面的绝缘部分和连接到半导体芯片的多个电极。每个电极具有由绝缘部分包围并位于其上布置有布线部分3A和3B的主体2的侧表面的端面。布线部分3A和3B连接到多个层部分的多个电极的端面以及多个第一和第二端子22A和22B。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2010016373A Method of manufacturing layered chip package 有权
标题翻译：制造分层芯片包装的方法
公开(公告)号：JP2010016373A
公开(公告)日：2010-01-21
申请号：JP2009148253
申请日：2009-06-23
申请人： Headway Technologies Inc , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/544 , H01L21/67005 , H01L23/49805 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/24011 , H01L2224/24226 , H01L2224/274 , H01L2224/48091 , H01L2224/49 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a means of mass-producing layered chip packages inexpensively in a short time. SOLUTION: A manufacturing method for a layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures 110 each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: bonding a first pre-polishing substructure to a jig 112 such that a first surface of the first pre-polishing substructure faces the jig 112; forming a first substructure 110 by polishing a second surface of the first pre-polishing substructure; bonding a second pre-polishing substructure to the first substructure 110 such that a first surface 109a of the second pre-polishing substructure 109 faces the polished surface 110b of the first substructure 110; and forming a second substructure 109 by polishing a second surface 109a of the second pre-polishing substructure 109. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了在短时间内廉价地提供批量生产分层芯片封装的方法。解决方案：一种分层芯片封装的制造方法，包括以下步骤：通过堆叠多个子结构110来制造分层子结构，每个子结构110包括对应于层状芯片封装的多个层部分的多个层部分; 以及通过使用层状子结构制造多个分层芯片封装。制造层状子结构的步骤包括：将第一预抛光子结构结合到夹具112，使得第一预抛光下结构的第一表面面向夹具112; 通过抛光第一预抛光子结构的第二表面来形成第一子结构110; 将第二预抛光子结构结合到第一子结构110，使得第二预抛光子结构109的第一表面109a面向第一子结构110的抛光表面110b; 以及通过抛光第二预抛光子结构109的第二表面109a形成第二子结构109.权利要求：（C）2010，JPO＆INPIT

9. 发明专利

JP2010004048A Layered chip package and method of manufacturing same 有权
标题翻译：层状芯片包装及其制造方法
公开(公告)号：JP2010004048A
公开(公告)日：2010-01-07
申请号：JP2009148252
申请日：2009-06-23
申请人： Headway Technologies Inc , Tdk Corp , Tdk株式会社 , ヘッドウェイテクノロジーズインコーポレイテッド
发明人： SASAKI YOSHITAKA , ITO HIROYUKI , HARADA TATSUYA , OKUZAWA NOBUYUKI , SUEKI SATORU
IPC分类号： H01L25/10 , H01L21/56 , H01L23/12 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/11 , H01L25/18
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/544 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/95 , H01L25/0657 , H01L2221/68359 , H01L2223/5442 , H01L2223/54426 , H01L2224/24145 , H01L2224/48463 , H01L2224/4943 , H01L2225/06551 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/181 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To make it possible to mass-product a laminated chip package at low cost, in a short time. SOLUTION: A laminated chip package 1 includes its body 2, including a plurality of hierarchical parts 11 to 18 and wires 3A and 3B arranged on the side surface of the body 2. Each hierarchical part includes a semiconductor chip, an insulating part that covers at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating part has an end surface, arranged on the side surface of the body 2 in which the wires 3A and 3B are arranged. Each electrode has an end surface arranged on the side surface of the body 2, in which the wires 3A and 3B are arranged and surrounded by the insulating part. When the laminated chip package 1 is manufactured, a semiconductor wafer is processed, a plurality of semiconductor chip scheduled parts arranged in an array are formed, one or more grooves extending so as to neighbor at least one semiconductor chip scheduled part are formed, an insulating layer is formed so as to fill in the groove; and further, a plurality of electrodes are formed and a fundamental structure is manufactured. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了能够在短时间内以低成本批量生产层压芯片封装成为可能。解决方案：层叠芯片封装1包括其主体2，其包括多个分层部分11至18以及布置在主体2的侧表面上的导线3A和3B。每个分层部分包括半导体芯片，绝缘部分覆盖半导体芯片的至少一个侧表面以及连接到半导体芯片的多个电极。绝缘部具有设置在主体2的配置有导线3A，3B的侧面的端面。每个电极具有布置在主体2的侧表面上的端面，其中导线3A和3B布置并被绝缘部分包围。当制造层压芯片封装1时，处理半导体晶片，形成排列成阵列的多个半导体芯片预定部分，形成一个或多个延伸以邻近至少一个半导体芯片预定部分的凹槽，绝缘形成层以填充凹槽; 此外，形成多个电极，并且制造基本结构。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2005057211A Coil component 审中-公开
标题翻译：线圈组件
公开(公告)号：JP2005057211A
公开(公告)日：2005-03-03
申请号：JP2003289244
申请日：2003-08-07
申请人： Tdk Corp , Tdk株式会社
发明人： YOSHIDA MAKOTO , ITO TOMOKAZU , KONNO TADASHIGE , OKUZAWA NOBUYUKI
IPC分类号： H01F17/00 , H01F27/00
摘要： PROBLEM TO BE SOLVED: To provide a coil component that can makes uniform the impedance of first and second coil conductors although the component has a simple constitution.
SOLUTION: The first and second coil conductors 5 and 7 are disposed between first and second magnetic substrates in spirally wound states. The coil conductors 5 and 7 respectively contain first sections 5a and 7a which are disposed in parallel with each other at a prescribed interval on a first insulating layer and second sections 5b and 7b which three-dimensionally intersect each other. The coil conductors 5 and 7 have two pairs of second sections 5b and 7b. In addition, the coil conductors 5 and 7 intersect each other twice in their mid-courses when the conductors 5 and 7 are viewed from the direction perpendicular to the principal surface of the first magnetic substrate (second magnetic substrate).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够使第一和第二线圈导体的阻抗均匀的线圈部件，尽管该部件具有简单的结构。解决方案：第一和第二线圈导体5和7以螺旋卷绕状态设置在第一和第二磁性基板之间。线圈导体5和7分别包含在第一绝缘层上以规定间隔彼此平行地设置的第一部分5a和7a以及三维地彼此相交的第二部分5b和7b。线圈导体5和7具有两对第二部分5b和7b。此外，当从与第一磁性基板（第二磁性基板）的主表面垂直的方向观察导体5和7时，线圈导体5和7在它们的中间横列中彼此相交两次。版权所有（C）2005，JPO＆NCIPI

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