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1. 发明授权

US08537042B2 Multi-bit digital to analogue converter and a delta-sigma analogue to digital converter 有权
标题翻译：多位数模转换器和一个delta-sigma模数转换器
公开(公告)号：US08537042B2
公开(公告)日：2013-09-17
申请号：US13359741
申请日：2012-01-27
申请人： Hashem Zare-Hoseini , Peter Williams
发明人： Hashem Zare-Hoseini , Peter Williams
IPC分类号： H03M1/66 , H03M3/02
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464
摘要： The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC.
摘要翻译：本发明涉及一种多位数模转换器（DAC）以及采用这种DAC的Δ-Σ模数转换器。 DAC具有多位输入，用于处理在输入端接收的输入信号的多个元件和用于根据输入信号选择一个或多个DAC元件来处理该信号的选择器。 DAC具有用于控制选择器的控制装置，使得如果DAC的输入在预定时间段内低于预定电平，则选择器仅可操作以仅选择DAC单元中的一个来处理输入信号。还公开了采用这种DAC的Δ-Σ模数转换器（ADC）。

2. 发明申请

US20130141176A1 Highly Linear-Gain Oscillator 有权
标题翻译：高线性增益振荡器
公开(公告)号：US20130141176A1
公开(公告)日：2013-06-06
申请号：US13310156
申请日：2011-12-02
申请人： Shuja Hussain Andrabi , Hashem Zare-Hoseini
发明人： Shuja Hussain Andrabi , Hashem Zare-Hoseini
IPC分类号： H03B5/12
CPC分类号： H04L27/0014 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1278 , H03B2200/0092 , H03J2200/10 , H03L7/099 , H04L2027/0016 , H04L2027/0055 , H04L2027/0071
摘要： A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance.
摘要翻译：可变频率振荡器包括具有第一电感的电感单元，耦合在电感单元两端的第一可变电容器和耦合在电感单元的一部分上的第二可变电容器。由第二可变电容器耦合的电感单元的部分的电感是第一电感的一部分。

3. 发明授权

US09184713B2 Low distortion amplifier 有权
标题翻译：低失真放大器
公开(公告)号：US09184713B2
公开(公告)日：2015-11-10
申请号：US13141045
申请日：2009-11-26
申请人： Hashem Zare-Hoseini
发明人： Hashem Zare-Hoseini , Ian Sabberton
IPC分类号： H03F1/36 , H03G1/04 , H03G1/00 , H03F1/32
CPC分类号： H03G1/04 , H03F1/3211 , H03G1/0088
摘要： A variable gain amplifier circuit (200) comprising an amplifier element (202) having an input (208, 210) and an output (220, 222); a feedback loop (224, 226) having a feedback impedance (228, 230) connected between the input (208, 210) and output (232, 234) of the amplifier element (202); an input branch (212, 214) having an input resistance connected between an input of the variable gain amplifier circuit and the input (208, 210) of the amplifier element (202); and a plurality of switches for selecting a gain of the variable gain amplifier circuit (200); characterised in that the variable gain amplifier circuit (200) further comprises an intermediate element (204) having an input and an output, the input being connected to a node between one of the switches and the feedback impedance (228, 230), such that the output can provide a signal which can be used to attenuate a signal component in the output (220, 222) of the amplifier element (202) caused by a non-linearity in the plurality of switches.
摘要翻译：一种包括具有输入（208,210）和输出（220,222）的放大器元件（202）的可变增益放大器电路（200）。具有连接在放大器元件（202）的输入（208,210）和输出（232,234）之间的反馈阻抗（228,230）的反馈回路（224,226）。输入分支（212,214），其具有连接在所述可变增益放大器电路的输入端和所述放大器元件（202）的输入端（208,210）之间的输入电阻; 以及用于选择可变增益放大器电路（200）的增益的多个开关; 其特征在于，所述可变增益放大器电路（200）还包括具有输入和输出的中间元件（204），所述输入连接到所述开关之一和所述反馈阻抗（228,230）之间的节点，使得输出可以提供可以用于衰减由多个开关中的非线性引起的放大器元件（202）的输出（220,222）中的信号分量的信号。

4. 发明申请

US20140028374A1 SPUR REDUCTION CIRCUIT 有权
标题翻译：减少电路
公开(公告)号：US20140028374A1
公开(公告)日：2014-01-30
申请号：US13561507
申请日：2012-07-30
申请人： Hashem Zare-Hoseini , Shuja Hussain Andrabi
发明人： Hashem Zare-Hoseini , Shuja Hussain Andrabi
IPC分类号： G06G7/14
CPC分类号： H03M7/3008
摘要： A circuit for modulating an input signal including a dither signal generator configured to generate a first dither signal having a maximum amplitude, a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal, and a summer configured to sum the dither signal with the deamplified input signal.
摘要翻译：一种用于调制包括被配置为产生具有最大幅度的第一抖动信号的抖动信号发生器的输入信号的电路，被配置为减小所述输入信号的幅度以便产生具有可比较的最大振幅的去放大输入信号的去放大器到抖动信号的最大幅度，以及加法器，用于将抖动信号与去放大的输入信号相加。

5. 发明授权

US07561089B2 Digital to analogue conversion 失效
标题翻译：数模转换
公开(公告)号：US07561089B2
公开(公告)日：2009-07-14
申请号：US11793583
申请日：2005-12-14
申请人： Hashem Zare-Hoseini , Izzet Kale , Richard Charles Spicer Morling
发明人： Hashem Zare-Hoseini , Izzet Kale , Richard Charles Spicer Morling
IPC分类号： H03M1/66
CPC分类号： H03M3/372 , H03M3/464 , H03M3/502
摘要： A method of Digital to Analogue conversion of an input signal Do for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (Vref) during a first phase (φ) of a clock signal, discharging the capacitor during a second phase (φ2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal Do. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.
摘要翻译：一种用于抑制Delta-Sigma模数转换器或D类放大器中的时钟抖动的影响的输入信号Do的数模转换方法包括在第一时间段期间将电容器充电到参考电压值（Vref）相位（phi），在时钟信号的第二阶段（phi2）期间对电容器进行放电，其中响应于电容器上的电压，在第二阶段的第一部分中，偏置晶体管对放电进行调节以提供大致恒定的放电电流，并且在第二相的第二部分中调节以在第二相结束之前快速地放电电容器; 并提供作为放电电流和输入信号Do的函数的输出（Ud，OUT）。输出信号Ud可以作为反馈信号施加到Δ-Σ转换器中的环路滤波器。或者，输出可以表示D类放大器的输出。

6. 发明授权

US09705712B2 Highly linear-gain oscillator 有权
公开(公告)号：US09705712B2
公开(公告)日：2017-07-11
申请号：US13310156
申请日：2011-12-02
申请人： Shuja Hussain Andrabi , Hashem Zare-Hoseini
发明人： Shuja Hussain Andrabi , Hashem Zare-Hoseini
IPC分类号： H03B5/08 , H04L27/00 , H03B5/12 , H03L7/099
CPC分类号： H04L27/0014 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1278 , H03B2200/0092 , H03J2200/10 , H03L7/099 , H04L2027/0016 , H04L2027/0055 , H04L2027/0071
摘要： A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance.

7. 发明授权

US08730076B2 Spur reduction circuit 有权
标题翻译：减速电路
公开(公告)号：US08730076B2
公开(公告)日：2014-05-20
申请号：US13561507
申请日：2012-07-30
申请人： Hashem Zare-Hoseini , Shuja Hussain Andrabi
发明人： Hashem Zare-Hoseini , Shuja Hussain Andrabi
IPC分类号： H03M1/20
CPC分类号： H03M7/3008
摘要： A circuit for modulating an input signal including a dither signal generator configured to generate a first dither signal having a maximum amplitude, a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal, and a summer configured to sum the dither signal with the deamplified input signal.
摘要翻译：一种用于调制包括被配置为产生具有最大幅度的第一抖动信号的抖动信号发生器的输入信号的电路，被配置为减小所述输入信号的幅度以便产生具有可比较的最大振幅的去放大输入信号的去放大器到抖动信号的最大幅度，以及加法器，用于将抖动信号与去放大的输入信号相加。

8. 发明授权

US08279099B2 Delta-sigma analogue-to-digital converters 有权
标题翻译： Delta-sigma模数转换器
公开(公告)号：US08279099B2
公开(公告)日：2012-10-02
申请号：US12836078
申请日：2010-07-14
申请人： Hashem Zare-Hoseini
发明人： Hashem Zare-Hoseini
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03M3/424 , H03M3/438
摘要： An integrator based on an amplifier having a capacitive element connected between the input and the output of the amplifier, with a resistive element connected in series with the capacitive element. Integrators of this type can be used in feed-forward structures of delta-sigma analogue-to-digital converters in order to avoid the need for adders to combine the outputs of parallel signal paths in the feed-forward structure.
摘要翻译：一种基于放大器的积分器，其具有连接在放大器的输入和输出端之间的电容元件，电阻元件与电容元件串联连接。这种类型的积分器可以用于Δ-Σ模拟 - 数字转换器的前馈结构，以避免加法器在前馈结构中组合并行信号路径的输出。

9. 发明申请

US20080106447A1 Digital to Analogue Conversion 失效
标题翻译：数字到模拟转换
公开(公告)号：US20080106447A1
公开(公告)日：2008-05-08
申请号：US11793583
申请日：2005-12-14
申请人： Hashem Zare-Hoseini , Izzet Kale , Richard Charles Spicer Morling
发明人： Hashem Zare-Hoseini , Izzet Kale , Richard Charles Spicer Morling
IPC分类号： H03M1/66 , H03M1/00 , H03M3/00
CPC分类号： H03M3/372 , H03M3/464 , H03M3/502
摘要： A method of Digital to Analogue conversion of an input signal Do for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (Vref) during a first phase (φ) of a clock signal, discharging the capacitor during a second phase (φ2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal Do. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.
摘要翻译：用于抑制Delta-Sigma模数转换器或D类放大器中的时钟抖动的影响的用于输入信号D OUT的数模转换的方法包括将电容器充电到参考在时钟信号的第一阶段（phi）期间的电压值（V SUB ref），在时钟信号的第二阶段（phi <2> 2 ）期间对电容器放电，其中，在第二相的第一部分响应于电容器上的电压的偏置晶体管来调节放电，以提供近似恒定的放电电流，并且在第二相的第二部分中被调节以在端部之前快速放电电容器的第二阶段; 并提供作为放电电流和输入信号D OUT的函数的输出（U SUB，OUT）。输出信号U SUB可以作为反馈信号施加到Δ-Σ转换器中的环路滤波器。或者，输出可以表示D类放大器的输出。

10. 发明授权

US08456339B2 Delta sigma analogue to digital converter 有权
标题翻译： Delta西格玛模数转换器
公开(公告)号：US08456339B2
公开(公告)日：2013-06-04
申请号：US12985068
申请日：2011-01-05
申请人： Hashem Zare-Hoseini
发明人： Hashem Zare-Hoseini
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03M3/424 , H03M3/452 , H03M3/454 , H03M3/456
摘要： A delta sigma analogue to digital converter comprising: an integrator having first and second differential inputs for receiving an input analogue signal, the integrator having differential outputs; a quantiser having first and second differential inputs which receive signals output by the integrator, and an output which provides a digital output signal of the delta sigma analogue to digital converter, and a digital to analogue converter. The digital to analogue converter has an input which is connected to an output of the delta sigma analogue to digital converter, and first and second differential outputs. The first output of the digital to analogue converter is connected to the first input of the integrator such that if the second output of the digital to analogue converter is not connected to the second input of the integrator and the second input of the integrator is connected to a fixed reference voltage the delta sigma analogue to digital converter is able to operate in a single-ended mode.
摘要翻译：一种ΔΣ模数转换器，包括：具有用于接收输入模拟信号的第一和第二差分输入的积分器，该积分器具有差分输出; 具有接收由积分器输出的信号的第一和第二差分输入以及提供Δ-Σ模数转换器的数字输出信号的输出端和数模转换器的量化器。数模转换器具有连接到Δ-Σ模数转换器的输出的输入端以及第一和第二差分输出端。数模转换器的第一个输出端连接到积分器的第一个输入端，使得如果数模转换器的第二个输出没有连接到积分器的第二个输入端，并且积分器的第二个输入端连接到固定的参考电压，Δ西格玛模数转换器能够以单端模式工作。

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