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1. 发明申请

US20060013212A1 Port aggregation across stack of devices 审中-公开
标题翻译：端口堆叠的设备端口聚合
公开(公告)号：US20060013212A1
公开(公告)日：2006-01-19
申请号：US10890894
申请日：2004-07-13
申请人： Hartej Singh , Muraleedhara Navada , Miguel Guerrero
发明人： Hartej Singh , Muraleedhara Navada , Miguel Guerrero
IPC分类号： H04L12/56
CPC分类号： H04L45/04
摘要： Techniques for receiving a packet at a first packet forwarding device in a stack of packet forwarding devices, providing a port aggregation table having a plurality of entries, wherein at least one entry identifies a plurality of ports associated with at least two packet forwarding devices in the stack, and using the packet and the port aggregation table to select a port of a packet forwarding device in the stack for sending the packet to a device external to the stack.
摘要翻译：用于在分组转发设备的堆叠中的第一分组转发设备处接收分组的技术，提供具有多个条目的端口聚合表，其中至少一个条目标识与所述至少两个分组转发设备相关联的多个端口并且使用分组和端口聚合表来选择堆栈中的分组转发设备的端口，以将分组发送到堆栈外部的设备。

2. 发明申请

US20050220013A1 Adaptable traffic control for variable port speed connectivity device 失效
标题翻译：可变端口速度连接设备的适应性流量控制
公开(公告)号：US20050220013A1
公开(公告)日：2005-10-06
申请号：US10813958
申请日：2004-03-31
申请人： Hartej Singh , Muraleedhara Navada
发明人： Hartej Singh , Muraleedhara Navada
IPC分类号： H04L12/26 , H04L12/64
CPC分类号： H04L12/64
摘要： According to embodiments of the present invention, an adaptable traffic control system, method, article of manufacture, and apparatus receive a user-programmed value representing an amount of target traffic allowed through a connectivity device port and a user-programmed value representing a time interval during which to receive the allowed amount of target traffic. The two values define a percentage of target traffic allowed through the port for a particular port speed. One embodiment determines that port speed changed by a factor of N, scales the time interval by a factor of 1/N, and based on the allowed amount of target traffic and the scaled time interval, drops incoming target traffic when the received percentage of incoming target traffic is equal to (or greater than) the defined percentage of target traffic allowed through the port.
摘要翻译：根据本发明的实施例，可适应的交通控制系统，方法，制品和设备接收表示通过连接设备端口允许的目标通信量的用户编程值和表示时间间隔的用户编程值在此期间接收允许的目标流量。这两个值定义了特定端口速度通过端口允许的目标流量的百分比。一个实施例确定端口速度改变了N倍，将时间间隔缩小1 / N，并且基于允许的目标业务量和缩放时间间隔，当接收到的进入百分比目标流量等于（或大于）通过端口允许的目标流量的定义百分比。

3. 发明申请

US20060117114A1 Staggering memory requests 审中-公开
标题翻译：令人震惊的内存请求
公开(公告)号：US20060117114A1
公开(公告)日：2006-06-01
申请号：US10998860
申请日：2004-11-29
申请人： Rohit Verma , Muraleedhara Navada , Miguel Guerrero , Ashwani Oberai
发明人： Rohit Verma , Muraleedhara Navada , Miguel Guerrero , Ashwani Oberai
IPC分类号： G06F3/00
CPC分类号： G06F13/1615
摘要： A method according to one embodiment may include transmitting a plurality of packets through control pipeline circuitry of an integrated circuit of a switch. The control pipeline circuitry may be capable of making a plurality of memory requests to memory of the switch in response to the plurality of packets. The method may further comprise staggering the plurality of memory requests so that each of the plurality of memory requests occurs during a different one of a plurality of time slots. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括通过开关的集成电路的控制流水线电路传输多个分组。响应于多个分组，控制流水线电路可以能够对交换机的存储器进行多个存储器请求。该方法还可以包括交错多个存储器请求，使得多个存储器请求中的每一个在多个时隙中的不同时隙期间发生。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

4. 发明申请

US20050138276A1 Methods and apparatus for high bandwidth random access using dynamic random access memory 审中-公开
标题翻译：使用动态随机存取存储器进行高带宽随机访问的方法和装置
公开(公告)号：US20050138276A1
公开(公告)日：2005-06-23
申请号：US10742021
申请日：2003-12-17
申请人： Muraleedhara Navada , Rohit Verma , Miguel Guerrero
发明人： Muraleedhara Navada , Rohit Verma , Miguel Guerrero
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16
CPC分类号： G06F13/1647 , G06F12/06
摘要： The inventive subject matter provides various apparatus and methods to perform high-speed memory read accesses on dynamic random access memories (“DRAMs”) for read-intensive memory applications. In an embodiment, at least one input/output (“I/O”) channel of a memory controller is coupled to a pair of DRAM chips via a common address/control bus and via two independent data busses. Each DRAM chip may include multiple internal memory banks. In an embodiment, identical data is stored in each of the DRAM banks controlled by a given channel. In another embodiment, data is substantially uniformly distributed in the DRAM banks controlled by a given channel, and read accesses are uniformly distributed to all of such banks. Embodiments may achieve 100% read utilization of the I/O channel by overlapping read accesses from alternate banks from the DRAM pair.
摘要翻译：本发明主题提供用于对用于读取密集型存储器应用的动态随机存取存储器（“DRAM”）执行高速存储器读取访问的各种装置和方法。在一个实施例中，存储器控制器的至少一个输入/输出（“I / O”）通道经由公共地址/控制总线和经由两个独立的数据总线耦合到一对DRAM芯片。每个DRAM芯片可以包括多个内部存储器组。在一个实施例中，相同的数据被存储在由给定信道控制的每个DRAM组中。在另一个实施例中，数据基本均匀地分布在由给定信道控制的DRAM组中，并且读取访问被均匀分布到所有这些存储体。实施例可以通过重叠来自DRAM对的备用组的读取访问来实现I / O通道的100％的读取利用率。

5. 发明授权

US07328359B2 Technique to create link determinism 有权
标题翻译：技术创造链接决定论
公开(公告)号：US07328359B2
公开(公告)日：2008-02-05
申请号：US10897225
申请日：2004-07-21
申请人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
发明人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
IPC分类号： G06F1/04 , G06F1/12 , G06F5/00 , G06F13/42 , H04L7/00
CPC分类号： G06F13/4273 , G06F5/06
摘要： A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.
摘要翻译：一种促进点对点（PtP）网络中总线代理之间确定性的技术。更具体地，本发明的实施例涉及补偿公共系统接口（CSI）总线代理的PtP网络内的链路延迟，数据偏移和时钟偏移的技术。

6. 发明申请

US20060072571A1 Integrated circuit capable of routing multicast data packets using device vectors 失效
标题翻译：集成电路能够使用设备向量路由组播数据包
公开(公告)号：US20060072571A1
公开(公告)日：2006-04-06
申请号：US10953083
申请日：2004-09-29
申请人： Muraleedhara Navada , Hitesh Rastogi
发明人： Muraleedhara Navada , Hitesh Rastogi
IPC分类号： H04L12/56
CPC分类号： H04L12/18
摘要： A method according to one embodiment may include communicating with at least one external device using at least one port. The method may also include storing a multicast data packet and a master device vector in memory. The method may also include de-queueing the master device vector from memory, generating at least one additional device vector based at least in part on the master device vector, and transmitting the multicast data packet and at least one additional device vector to at least one external device via at least one port. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括使用至少一个端口与至少一个外部设备进行通信。该方法还可以包括将多播数据分组和主设备向量存储在存储器中。该方法还可以包括：从存储器去除排队主设备向量，至少部分地基于主设备向量生成至少一个附加设备向量，以及将多播数据分组和至少一个附加设备向量发送到至少一个外部设备通过至少一个端口。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

7. 发明申请

US20050149604A1 Packet tracing 有权
标题翻译：数据包跟踪
公开(公告)号：US20050149604A1
公开(公告)日：2005-07-07
申请号：US10740383
申请日：2003-12-17
申请人： Muraleedhara Navada
发明人： Muraleedhara Navada
IPC分类号： G06F15/16 , H04L12/26 , H04L29/06
CPC分类号： H04L43/10 , H04L69/12
摘要： A method of packet tracing includes triggering tracer devices. Each tracer device corresponds to an associated processing stage within a packet processor. The method also includes storing an indication after a packet completes an associated processing stage. The method may further include sending contents of a register to an application.
摘要翻译：包跟踪的方法包括触发跟踪设备。每个跟踪设备对应于分组处理器内的相关处理阶段。该方法还包括在分组完成相关联的处理阶段之后存储指示。该方法还可以包括向应用发送寄存器的内容。

8. 发明申请

US20080065924A1 Technique to create link determinism 有权
公开(公告)号：US20080065924A1
公开(公告)日：2008-03-13
申请号：US11978849
申请日：2007-10-30
申请人： Tim Frodsham , Michael Tripp , David O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David Dunning , Theodore Schoenborn
发明人： Tim Frodsham , Michael Tripp , David O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David Dunning , Theodore Schoenborn
IPC分类号： G06F1/12
CPC分类号： G06F13/4273 , G06F5/06
摘要： A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

9. 发明申请

US20070071083A1 Equalizing a transmitter 有权
标题翻译：变送器均衡
公开(公告)号：US20070071083A1
公开(公告)日：2007-03-29
申请号：US11237118
申请日：2005-09-28
申请人： Karthisha Canagasaby , Muraleedhara Navada , Sanjay Dabral
发明人： Karthisha Canagasaby , Muraleedhara Navada , Sanjay Dabral
IPC分类号： H03H7/30
CPC分类号： H04L25/0282 , H04L25/0276 , H04L25/0288
摘要： In one embodiment, the present invention includes a method for associating a first plurality of current sources with a first tap coefficient and associating a second plurality of current sources with a second tap coefficient. A first plurality of output switches coupled to the first plurality of current sources is gated using the first tap coefficient and a second plurality of output switches coupled to the second plurality of current sources is gated using the second tap coefficient. In such manner, the first and second plurality of equalized current sources may be driven onto an interconnect. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于将第一多个电流源与第一抽头系数相关联并将第二多个电流源与第二抽头系数相关联的方法。耦合到第一多个电流源的第一多个输出开关使用第一抽头系数进行门控，并且使用第二抽头系数选择耦合到第二多个电流源的第二多个输出开关。以这种方式，第一和第二多个均衡的电流源可以被驱动到互连上。描述和要求保护其他实施例。

10. 发明授权

US07111093B2 Ping-pong buffer system having a buffer to store a subset of data from a data source 失效
标题翻译：乒乓缓冲系统具有缓存以存储来自数据源的数据子集
公开(公告)号：US07111093B2
公开(公告)日：2006-09-19
申请号：US10601499
申请日：2003-06-23
申请人： Muraleedhara Navada , Sreenath Kurupati
发明人： Muraleedhara Navada , Sreenath Kurupati
IPC分类号： G06F3/00
CPC分类号： G06F5/16
摘要： According to some embodiments, a ping-pong buffer system has a buffer that stores a subset of data from a data source.
摘要翻译：根据一些实施例，乒乓缓冲系统具有存储来自数据源的数据子集的缓冲器。

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