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1. 发明授权

US07324500B1 Router network protection using multiple facility interfaces 失效
标题翻译：路由器网络保护使用多个设施接口
公开(公告)号：US07324500B1
公开(公告)日：2008-01-29
申请号：US09703027
申请日：2000-10-31
申请人： Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Thomas C. McDermott, III , Gregory S. Palmer
发明人： Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Thomas C. McDermott, III , Gregory S. Palmer
IPC分类号： H04L12/28
CPC分类号： H04L45/24 , H04L45/00 , H04L45/22 , H04L49/557
摘要： A router line card is partitioned to separate the packet forwarding functions from physical port interfacing. For each packet forwarding card, at least one redundant port interface is provided. Identical input packets are transmitted via these redundant input port interfaces, one of which is eventually selected based on, for example, SONET standard criteria. If there is a failure, the router selects the interface path that is operating properly and rejects the path containing a failed element. Thus, the router decides locally how to correct the problem internally. Moreover, following an equipment failure the now offline failed interface path can be replaced, while the equipment remains in service using the duplicated interface path. The system can be restored to full duplex operation without affecting the existing traffic, providing for a hot replacement of a failed path. Because the interfaces are separate, a failed module can be renewed and replaced while the equipment is in service. If a failure occurs in an interface card between two peer routers, then packets flow between the two routers uninterrupted from exactly the same previous ports on one router to the same previous ports on the second router, using the same Internet protocol addresses as existed prior to the switching.
摘要翻译：路由器线路卡被划分为将数据包转发功能与物理端口接口分开。对于每个分组转发卡，提供至少一个冗余端口接口。相同的输入数据包通过这些冗余输入端口接口进行传输，其中一个输入端口最终根据例如SONET标准标准进行选择。如果发生故障，则路由器选择正常运行的接口路径，并拒绝包含故障元素的路径。因此，路由器在本地决定如何在内部纠正问题。此外，在设备故障之后，现在离线失败的接口路径可以被替换，而设备使用复制的接口路径保持服务。系统可以恢复到全双工操作，而不影响现有流量，从而为故障路径进行热替换。由于接口是分开的，故障模块可以在设备投入使用时更新并更换。如果在两个对等路由器之间的接口卡中发生故障，则两台路由器之间的数据包将不间断地从一个路由器上的完全相同的以前的端口流向第二个路由器上相同的以前的端口，使用与之前存在的相同的Internet协议地址切换。

2. 发明授权

US08315175B2 Router switch fabric protection using forward error correction 有权
标题翻译：路由器交换矩阵保护采用前向纠错
公开(公告)号：US08315175B2
公开(公告)日：2012-11-20
申请号：US10981841
申请日：2004-11-05
申请人： Thomas C. McDermott, III , Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Jim Kleiner , Gregory S. Palmer , Keith W. Shaw , David Traylor , Dean E. Walker
发明人： Thomas C. McDermott, III , Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Jim Kleiner , Gregory S. Palmer , Keith W. Shaw , David Traylor , Dean E. Walker
IPC分类号： H04L12/26
CPC分类号： H04Q11/0005 , H04J2203/0057 , H04L49/1523 , H04L49/208 , H04L49/254 , H04L49/357 , H04L2012/5627 , H04Q11/0066 , H04Q2011/0043
摘要： Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric. Under error-free normal conditions, however, the PFMs select a chunk arbitrarily from a default switch fabric. In this way, each chunk in real time is selected from a non-defective source and is thus guaranteed to be error free. Accordingly, if a switch fabric fails, no information chunks are lost anywhere in the system.
摘要翻译：代替替代地仅使用冗余对的一个结构或另一个结构，两个结构同时发送重复信息，使得每个分组转发模块（PFM）同时接收两个结构的输出。实时地，内部光学模块（IOM）分析从工作的零交换结构出来的每个信息块; 同时检查工作的一个重复交换矩阵的并行输出; 并且以逐块为基础比较来自两个交换结构的每个块的有效性。 IOM通过检查封装到每个块中的前向纠错（FEC）校验符号来实现。 FEC检查符号允许校正块内的预定数量的位错误。如果块不能被纠正，则IOM向下游的所有PFM提供指示该块是有缺陷的。在这种情况下，PFM从无缺陷的交换结构中选择一个块。然而，在无错误的正常条件下，PFM从默认的交换结构中任意选择一个块。以这种方式，从无缺陷源选择实时的每个块，并且因此被保证是无错误的。因此，如果交换机结构发生故障，系统中的任何地方都不会丢失任何信息块。

3. 发明授权

US06894970B1 Router switch fabric protection using forward error correction 失效
公开(公告)号：US06894970B1
公开(公告)日：2005-05-17
申请号：US09703064
申请日：2000-10-31
申请人： Thomas C. McDermott, III , Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Jim Kleiner , Gregory S. Palmer , Keith W. Shaw , David Traylor , Dean E. Walker
发明人： Thomas C. McDermott, III , Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Jim Kleiner , Gregory S. Palmer , Keith W. Shaw , David Traylor , Dean E. Walker
IPC分类号： H04L12/56 , H04Q11/00 , H04Q11/04 , H04L1/22 , H04L12/26
CPC分类号： H04Q11/0005 , H04J2203/0057 , H04L49/1523 , H04L49/208 , H04L49/254 , H04L49/357 , H04L2012/5627 , H04Q11/0066 , H04Q2011/0043
摘要： Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric. Under error-free normal conditions, however, the PFMs select a chunk arbitrarily from a default switch fabric. In this way, each chunk in real time is selected from a non-defective source and is thus guaranteed to be error free. Accordingly, if a switch fabric fails, no information chunks are lost anywhere in the system.

4. 发明授权

US06879559B1 Router line card protection using one-for-N redundancy 失效
标题翻译：路由器线卡保护采用一对一冗余
公开(公告)号：US06879559B1
公开(公告)日：2005-04-12
申请号：US09703043
申请日：2000-10-31
申请人： Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Jim Kleiner , Thomas C. McDermott, III , Gregory S. Palmer , Keith W. Shaw , David Traylor
发明人： Harry C. Blackmon , Tony M. Brewer , Harold W. Dozier , Jim Kleiner , Thomas C. McDermott, III , Gregory S. Palmer , Keith W. Shaw , David Traylor
IPC分类号： H04L12/56 , H04L1/22
CPC分类号： H04L45/28 , H04L45/00 , H04L45/583 , H04L49/552
摘要： Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds. Alternatively, protect line cards can routinely carry low priority traffic that is interruptible, allowing the protect line card to handle higher priority traffic previously carried by a failed working line card. This approach renders unnecessary engineering a network for less than full capacity to allow rerouting in the event of individual line card failure. Consequently, all data paths can be fully utilized. If a particular interface module on one data bus needs removal for maintenance, a duplicate data bus is available intact, allowing hot replacement of any working or protect interface module, even while a line card protection switch is in effect.
摘要翻译：路由器线路卡被分区，将数据包转发与外部或内部接口分离，并允许多个线路卡访问任何一组外部或内部数据路径。任何失败的工作线卡都可以用另一个线卡替代。特别地，接口侧的串行总线结构将保护组内的任何接口端口与该组的保护线路卡相互连接。增量容量允许保护线路卡执行数据包转发功能。线卡寻址和识别的逻辑映射提供对其他路由器线路卡和所有对等路由器透明的线路卡的本地管理保护倒换。一个N保护比，其中N是一个大于2的整数，可以经济实现，但提供足够的容量和可接受的保护开关时间在100毫秒以下。或者，保护线路卡可以常规地携带可中断的低优先级业务，从而允许保护线路卡处理先前由故障工作线路卡携带的较高优先级的业务。这种方法使不必要的工程网络满足不足的容量，以允许在单独的线路卡故障的情况下重新路由。因此，可以充分利用所有数据路径。如果一个数据总线上的特定接口模块需要拆卸维护，则重复的数据总线可以完整使用，即使在线卡保护开关有效时，也可以热插拔任何工作或保护接口模块。

5. 发明授权

US08279879B1 System and method for router data aggregation and delivery 失效
标题翻译：路由器数据汇总和传送的系统和方法
公开(公告)号：US08279879B1
公开(公告)日：2012-10-02
申请号：US12563844
申请日：2009-09-21
申请人： Tony M. Brewer , Harry C. Blackmon , Chris Davies , Harold W. Dozier , Thomas C. McDermott, III , Steven J. Wallach , Dean E. Walker , Lou Yeh
发明人： Tony M. Brewer , Harry C. Blackmon , Chris Davies , Harold W. Dozier , Thomas C. McDermott, III , Steven J. Wallach , Dean E. Walker , Lou Yeh
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04J3/0605 , H04L1/004 , H04L1/0083
摘要： A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format. “Break Bytes” and “Make Bytes” fields located at the beginning of a chunk preamble precondition an optical receiver to a proper state before the actual chunk arrives at the receiver.
摘要翻译：用于大规模，高数据吞吐量路由器的块格式包括前导码，其允许每个单独的块在检索块数据之前执行时钟和数据恢复。该格式包括一个包含特定于整个块的信息的块头。根据本格式的块可以包含多个分组段，每个段具有用于分组特定信息的其自己的分组报头。该格式提供加扰器种子，其允许加扰数据以获得良好的零和一个平衡以及最小的游程长度。可以随意选择任何特定块的可用扰码器种子，以避免恶意强制零和一种模式或运行长度的零位和零。有一个块循环冗余校验（CRC）以及前向纠错（FEC）字节来检测和/或校正任何错误，并且还能确保高度的数据和控制完整性。有利地，插入块格式本身的成帧符号允许接收电路识别或定位特定的块格式。位于块前导码开始处的Break Bytes和Make Byte字段将光接收器预先处理到在实际块到达接收机之前的适当状态。

6. 发明授权

US07613183B1 System and method for router data aggregation and delivery 有权
标题翻译：路由器数据汇总和传送的系统和方法
公开(公告)号：US07613183B1
公开(公告)日：2009-11-03
申请号：US09703038
申请日：2000-10-31
申请人： Tony M. Brewer , Harry C. Blackmon , Chris Davies , Harold W. Dozier , Thomas C. McDermott, III , Steven J. Wallach , Dean E. Walker , Lou Yeh
发明人： Tony M. Brewer , Harry C. Blackmon , Chris Davies , Harold W. Dozier , Thomas C. McDermott, III , Steven J. Wallach , Dean E. Walker , Lou Yeh
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04J3/0605 , H04L1/004 , H04L1/0083
摘要： A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There are forward error correction (FEC) bytes as well as a chunk cyclical redundancy check (CRC) to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format. “Break Bytes” and “Make Bytes” fields located at the beginning of a chunk preamble precondition an optical receiver to a proper state before the actual chunk arrives at the receiver.
摘要翻译：用于大规模，高数据吞吐量路由器的块格式包括前导码，其允许每个单独的块在检索块数据之前执行时钟和数据恢复。该格式包括一个包含特定于整个块的信息的块头。根据本格式的块可以包含多个分组段，每个段具有用于分组特定信息的其自己的分组报头。该格式提供加扰器种子，其允许加扰数据以获得良好的零和一个平衡以及最小的游程长度。存在前向纠错（FEC）字节以及块循环冗余校验（CRC）以检测和/或校正任何错误，并且还确保高度的数据和控制完整性。有利地，插入块格式本身的成帧符号允许接收电路识别或定位特定的块格式。在实际块到达接收机之前，将位于块前同步码开始处的“间隔字节”和“字节”字段将光接收器预处理到适当的状态。

7. 发明授权

US07058315B2 Fast decision threshold controller for burst-mode receiver 失效
公开(公告)号：US07058315B2
公开(公告)日：2006-06-06
申请号：US09974575
申请日：2001-10-09
申请人： Tony M. Brewer , Christopher P. Davies , Thomas C. McDermott, III , Allen F. Rozman
发明人： Tony M. Brewer , Christopher P. Davies , Thomas C. McDermott, III , Allen F. Rozman
IPC分类号： H04B3/20
CPC分类号： H04L25/062 , H04B10/695
摘要： A repetitive burst-mode input signal that has a dark time portion, a preamble portion, and a payload portion is converted into a limited output signal in accordance with a decision threshold level, which is controlled by selectively coupling an averaged value of the burst-mode data amplitude to the decision threshold level. The timing sequence for selectively coupling the averaged signal value is controlled such that the average value of the burst-mode signal acquired during the preamble portion of the burst-mode signal is applied to the decision threshold level during substantially all of the payload portion. The control circuit may incorporate a phase-locked loop, which locks onto the repetitive dark time frequency and in response synthesizes a switchable track enable signal that controls the timing sequence of the decision threshold level. The phase-locked loop can employ all-digital, analog, and/or hybrid digital/analog circuitry.

8. 发明授权

US4254492A Redundant clock system utilizing nonsynchronous oscillators 失效
标题翻译：冗余时钟系统利用非同步振荡器
公开(公告)号：US4254492A
公开(公告)日：1981-03-03
申请号：US25816
申请日：1979-04-02
申请人： Thomas C. McDermott, III
发明人： Thomas C. McDermott, III
IPC分类号： G04C13/04 , G04G7/00 , G06F11/16 , G04F8/00 , G04B17/12 , H03B27/00
CPC分类号： G06F11/1604 , G04C13/0409 , G04G7/00 , G06F11/1608 , G06F11/20
摘要： A clock system is disclosed having two identical clocks not synchronized with each other. Each of the clocks includes a circuit for selecting the output of one of the clocks as the present system output. Further, each clock includes logic for detecting errors in the operation of itself, and of the other. When an error is detected in the operation of the clock selected to be the present system output, a switchover sequence control switches the output signal of the nonselected clock to become the new system output. The switchover sequence control includes a feature which ensures that the interval between pulses in the system output is greater than a predetermined period in order to minimize detrimental effects on circuitry utilizing the clock system output.
摘要翻译：公开了一种具有彼此不同步的两个相同时钟的时钟系统。每个时钟包括用于选择其中一个时钟的输出作为当前系统输出的电路。此外，每个时钟包括用于检测其自身的操作中的错误的逻辑和另一个的逻辑。当在选择为当前系统输出的时钟的操作中检测到错误时，切换顺序控制切换非选定时钟的输出信号，成为新的系统输出。切换顺序控制包括确保系统输出中的脉冲之间的间隔大于预定周期的特征，以便最小化利用时钟系统输出的电路的不利影响。

9. 发明授权

US4602367A Method and apparatus for framing and demultiplexing multiplexed digital data 失效
标题翻译：用于对多路复用数字数据进行成帧和解复用的方法和装置
公开(公告)号：US4602367A
公开(公告)日：1986-07-22
申请号：US644489
申请日：1984-08-27
申请人： Thomas C. McDermott, III
发明人： Thomas C. McDermott, III
IPC分类号： H04J3/06 , H04L7/00
CPC分类号： H04J3/0608
摘要： If each data channel comprising a set of multiplexed data channels contains channel identity information, a single framing detector operating on one channel can provide a framing detection operation regardless of where the search is commenced thereby avoiding a search of all of the channels to obtain framing information. By having unique tag or identity bits incorporated in each of the multiplexed data channels, the timing problems for obtaining synchronized parallel output bits from each of the channels can be logically ascertained and the channels can be rerouted and individual channels of the rerouted channels can be time delayed to obtain the time synchronization.
摘要翻译：如果包括一组复用数据信道的每个数据信道包含信道身份信息，则在一个信道上操作的单个成帧检测器可以提供成帧检测操作，而不管搜索何时开始，从而避免搜索所有信道以获得帧信息。通过在每个多路复用的数据信道中具有唯一的标签或标识位，可以逻辑地确定从每个信道获得同步的并行输出位的定时问题，并且可以重新路由信道，并且重新路由的信道的各个信道可以是时间延迟获得时间同步。

10. 发明授权

US4549283A Digital time delay circuit with high speed and large delay capacity 失效
标题翻译：数字时延电路具有高速，大延时能力
公开(公告)号：US4549283A
公开(公告)日：1985-10-22
申请号：US529302
申请日：1983-09-06
申请人： Thomas C. McDermott, III
发明人： Thomas C. McDermott, III
IPC分类号： G06F12/06 , G11C7/00 , G11C8/00 , G11C13/00
CPC分类号： G11C8/00 , G06F12/0607 , G11C7/00
摘要： A delay circuit including an even number of memory devices, for example two, reading from one memory device, while writing to the other. Sequences of bit addresses are generated for writing and reading, with an offset between the sequences. For the case of two memory devices, each address sequence is applied alternately to the one and then the other memory device. Importantly, if each memory device has an even number n of storage locations, then, preferably, only (n-1) of these are used in the generated sequences of addresses. This has the result that the circuit can write to and read from all of the memory locations in the memory devices. Thus, the maximum delay possible in the circuit of the invention is nearly the total number of bits in the multiple memory devices, and the circuit is capable of handling data at the maximum operating rate of the memory devices.
摘要翻译：包括偶数个存储器件的延迟电路，例如两个，从一个存储器件读取，同时写入另一个。产生位地址的序列用于写入和读取，并且序列之间具有偏移量。对于两个存储器件的情况，每个地址序列交替地应用于一个存储器件和另一个存储器件。重要的是，如果每个存储器件具有偶数n个存储位置，则优选地，在所生成的地址序列中仅使用（n-1）个存储器。这导致电路可以写入存储器件中的所有存储器位置并从其读取。因此，本发明的电路中可能的最大延迟几乎是多个存储器件中的总位数，并且该电路能够以存储器件的最大工作速率处理数据。

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