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1. 发明申请

US20050216673A1 Method and apparatus handling locks 审中-公开
标题翻译：方法和设备处理锁
公开(公告)号：US20050216673A1
公开(公告)日：2005-09-29
申请号：US11131765
申请日：2005-05-17
申请人： Harish Kumar , Aravindh Baktha , Mike Upton , KS Venkatraman , Herbert Hum , Zhongying Zhang
发明人： Harish Kumar , Aravindh Baktha , Mike Upton , KS Venkatraman , Herbert Hum , Zhongying Zhang
IPC分类号： G06F9/312 , G06F9/318 , G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30087 , G06F9/30181 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F12/0815
摘要： A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.
摘要翻译：一种用于确定与锁定的加载指令相关联的属性并基于所述锁定加载指令的属性来选择锁定协议的方法和装置。还公开了一种用于并行执行与处理装置的多个线程相关联的各个锁定序列的方法。

2. 发明授权

US06922745B2 Method and apparatus for handling locks 有权
标题翻译：处理锁的方法和装置
公开(公告)号：US06922745B2
公开(公告)日：2005-07-26
申请号：US10139215
申请日：2002-05-02
申请人： Harish Kumar , Aravindh Baktha , Mike D. Upton , KS Venkatraman , Herbert H. Hum , Zhongying Zhang
发明人： Harish Kumar , Aravindh Baktha , Mike D. Upton , KS Venkatraman , Herbert H. Hum , Zhongying Zhang
IPC分类号： G06F9/312 , G06F9/318 , G06F9/38 , G06F12/08 , G06F12/14
CPC分类号： G06F9/3836 , G06F9/3004 , G06F9/30087 , G06F9/30181 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F12/0815
摘要： A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.
摘要翻译：一种用于确定与锁定的加载指令相关联的属性并基于所述锁定加载指令的属性来选择锁定协议的方法和装置。还公开了一种用于并行执行与处理装置的多个线程相关联的各个锁定序列的方法。

3. 发明申请

US20070083736A1 Instruction packer for digital signal processor 审中-公开
标题翻译：数字信号处理器指令包装机
公开(公告)号：US20070083736A1
公开(公告)日：2007-04-12
申请号：US11244564
申请日：2005-10-06
申请人： Aravindh Baktha , KS Venkatraman , Darrell Boggs
发明人： Aravindh Baktha , KS Venkatraman , Darrell Boggs
IPC分类号： G06F9/40
CPC分类号： G06F9/3857 , G06F9/30145 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： A digital signal processor which uses a RISC/CISC style front end and a VLIW style back end. Sequential ISA instructions are decoded into μops having a programmatic ordering. The μops are packed into a VLIW-like instruction packet according to a set of rules enforcing machine policy on e.g. data dependency, VLIW slot availability, maximum VLIW width, and so forth. Within the instruction packet, original program order is identified in case it is necessary to perform precise exception handling. The ISA code is executed as though it were on a RISC/CISC machine, but with VLIW style ILP efficiencies.
摘要翻译：数字信号处理器，采用RISC / CISC风格的前端和VLIW风格的后端。顺序ISA指令被解码成具有编程排序的muops。根据一组执行机器策略的规则，将muops打包成类VLIW指令包。数据依赖性，VLIW时隙可用性，最大VLIW宽度等。在指令包中，在需要执行精确异常处理的情况下，识别原始程序顺序。 ISA代码就像在RISC / CISC机器上一样执行，但是具有VLIW风格的ILP效率。

4. 发明授权

US07069424B2 Placing front instruction in replay loop to front to place side instruction into execution stream upon determination of criticality 失效
标题翻译：在确定关键性时，将前置指令放在重放循环中，将前置指令放置在执行流中
公开(公告)号：US07069424B2
公开(公告)日：2006-06-27
申请号：US10037023
申请日：2002-01-02
申请人： KS Venkatraman , Aravindh Baktha
发明人： KS Venkatraman , Aravindh Baktha
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3861
摘要： A method and apparatus for whacking a μOP based upon the criticality of that μOP. Also disclosed are embodiments of a method for determining the criticality of a μOP.
摘要翻译：基于该muOP的关键性来打击muOP的方法和装置。还公开了用于确定muOP的关键性的方法的实施例。

5. 发明申请

US20050138295A1 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US20050138295A1
公开(公告)日：2005-06-23
申请号：US10743134
申请日：2003-12-23
申请人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出，则重置状态位。

6. 发明授权

US07130965B2 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US07130965B2
公开(公告)日：2006-10-31
申请号：US10743134
申请日：2003-12-23
申请人： Per H. Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per H. Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或者从高速缓冲存储器中被逐出，则重置状态位。

7. 发明授权

US07085889B2 Use of a context identifier in a cache memory 有权
公开(公告)号：US07085889B2
公开(公告)日：2006-08-01
申请号：US10104815
申请日：2002-03-22
申请人： Per Hammarlund , Aravindh Baktha , Michael D Upton , Venkat K. S. Venkatraman
发明人： Per Hammarlund , Aravindh Baktha , Michael D Upton , Venkat K. S. Venkatraman
IPC分类号： G06F12/00
CPC分类号： G06F12/0842
摘要： A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

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