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1. 发明授权

US06611524B2 Programmable data packet parser 有权
标题翻译：可编程数据包解析器
公开(公告)号：US06611524B2
公开(公告)日：2003-08-26
申请号：US09340256
申请日：1999-06-30
申请人： Harish Devanagondi , James Sun
发明人： Harish Devanagondi , James Sun
IPC分类号： H04L1256
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9073 , H04L2012/5651 , H04Q11/0478
摘要： A data packet parser, for determining packet format, is substantially software controlled, to readily accommodate new or different formats, without the need for using a microprocessor for parsing. Comparisons are performed under the control of data stored in a database. By storing new or different data in the database, new or different packet formats can accommodated without the need for making hardware changes. In one embodiment, comparisons performed on various fields of the data packet result in setting or clearing bits of a signature word which identifies the packet format. The signature word can be used directly or indirectly such as forming the input argument of a ternary CAM, to provide a pointer to microcode which appropriately handles the data packet in the identified format.
摘要翻译：用于确定分组格式的数据分组解析器基本上是软件控制的，以容易地适应新的或不同的格式，而不需要使用微处理器进行解析。在数据库中存储的数据的控制下进行比较。通过将新的或不同的数据存储在数据库中，可以适应新的或不同的数据包格式，而无需进行硬件更改。在一个实施例中，对数据分组的各个领域执行的比较导致设置或清除标识分组格式的签名字的比特。签名字可以直接或间接使用，例如形成三元CAM的输入参数，以提供指向微代码的指针，该指针适当地处理所识别的格式的数据分组。

2. 发明授权

US07079525B1 Network switch having a hybrid switch architecture 失效
标题翻译：具有混合交换机架构的网络交换机
公开(公告)号：US07079525B1
公开(公告)日：2006-07-18
申请号：US09560673
申请日：2000-04-27
申请人： Adam Goldstein , David Smith , Harish Devanagondi , Hugh Barrass , Kamran Torabi , Rajesh Patil
发明人： Adam Goldstein , David Smith , Harish Devanagondi , Hugh Barrass , Kamran Torabi , Rajesh Patil
IPC分类号： H04L12/50
CPC分类号： H04L49/101 , H04L49/103 , H04L49/15 , H04L49/45
摘要： A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and re-collect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.
摘要翻译：具有混合交换机架构的网络交换机，其通过使用多个共享存储交换机结构和多个交叉交换结构来扩展以增加连接性，缓冲和带宽。每个交叉开关结构耦合到每个共享存储器交换结构。共享存储交换机结构被配置为存储和检索数据包。交叉开关结构被配置为向每个共享存储交换机结构分发和重新收集分组。具有混合交换机结构的网络交换机将分组从交叉交换结构分配到多个共享存储交换机结构，以在多个共享存储交换机结构之间共享分布式分组。

3. 发明授权

US07680097B1 Network switch having a hybrid switch architecture 有权
标题翻译：具有混合交换机架构的网络交换机
公开(公告)号：US07680097B1
公开(公告)日：2010-03-16
申请号：US11365214
申请日：2006-02-28
申请人： Adam Goldstein , David Smith , Harish Devanagondi , Hugh Barrass , Kamran Torabi , Rajesh Patil
发明人： Adam Goldstein , David Smith , Harish Devanagondi , Hugh Barrass , Kamran Torabi , Rajesh Patil
IPC分类号： H04J1/16
CPC分类号： H04L49/101 , H04L49/103 , H04L49/15 , H04L49/45
摘要： A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and recollect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.
摘要翻译：具有混合交换机架构的网络交换机，其通过使用多个共享存储交换机结构和多个交叉交换结构来扩展以增加连接性，缓冲和带宽。每个交叉开关结构耦合到每个共享存储器交换结构。共享存储交换机结构被配置为存储和检索数据包。交叉开关结构被配置为向每个共享存储交换机结构分发和重新收集分组。具有混合交换机结构的网络交换机将分组从交叉交换结构分配到多个共享存储交换机结构，以在多个共享存储交换机结构之间共享分布式分组。

4. 发明授权

US07317730B1 Queueing architecture and load balancing for parallel packet processing in communication networks 有权
标题翻译：通信网络中并行数据包处理的排队架构和负载平衡
公开(公告)号：US07317730B1
公开(公告)日：2008-01-08
申请号：US10269414
申请日：2002-10-11
申请人： Harish Devanagondi , Nicholas Bambos , Harish Belur , Richard Heaton , Majid Torabi
发明人： Harish Devanagondi , Nicholas Bambos , Harish Belur , Richard Heaton , Majid Torabi
IPC分类号： H04L12/28 , H04L12/54
CPC分类号： H04L49/9063 , H04L47/10 , H04L47/125 , H04L49/552 , H04L49/90 , H04L49/9094
摘要： A parallel packet processing queueing architecture and method are described. A packet is divided up into cells. A first or start processor queue is selected for the first cell. The following cells of the packet are then placed in the queues in a predetermined order. An example of a predetermined order is placing the cells in consecutive processor queues modulo (the number of processor queues) after the start processor. Such a predetermined order is illustrated in the context of a per Cell Contiguous Queueing (CCQ) architecture. The architecture provides benefits of alleviating the pre-processing and post-processing buffering burdens and decreasing the amount of information required for reassembly of the packet.
摘要翻译：描述并行包处理排队架构和方法。一个数据包被划分成单元格。为第一个单元选择第一个或启动处理器队列。然后将分组的以下小区以预定顺序放置在队列中。预定顺序的示例是在启动处理器之后将单元格模拟（处理器队列的数量）连续处理器队列。在每个单元连续排队（CCQ）架构的上下文中示出了这样的预定顺序。该架构提供了减轻预处理和后处理缓冲负担并减少重新组装分组所需的信息量的优点。

5. 发明申请

US20060206620A1 Method and apparatus for unified exception handling with distributed exception identification 有权
公开(公告)号：US20060206620A1
公开(公告)日：2006-09-14
申请号：US11431444
申请日：2006-05-09
申请人： Harish Devanagondi , Rajesh Patil , Sanjeev Mahalawat , Jianyong Sun
发明人： Harish Devanagondi , Rajesh Patil , Sanjeev Mahalawat , Jianyong Sun
IPC分类号： G06F15/16 , G06F13/28
CPC分类号： H03M13/09
摘要： A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an associated exception map in a memory of the apparatus. An exception detector at each processing stage detects whether any exception conditions apply to the data packet at the processing stage, and if so, a bit setter sets, modifies, or resets one or more bits in the exception map associated with exception conditions detected at the processing stage. An exception handler processes the exception map in response to the state of in the exception map after all the processing stages are complete.

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