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    • 1. 发明授权
    • Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
    • 电子设计自动化系统和方法利用具有环回连接的多个单元组来模拟端口电气特性
    • US06539536B1
    • 2003-03-25
    • US09496967
    • 2000-02-02
    • Harbinder SinghDenis MartinSrinivas AjjarapuRobert Walker
    • Harbinder SinghDenis MartinSrinivas AjjarapuRobert Walker
    • G06F1750
    • G06F17/5045
    • A computer implemented process and system for electronic design automation (EDA) using groups of multiple cells having loop-back connections for modeling port electrical characteristics. Multi-bit cells have multiple gates of the same function implemented within a same cell. Multi-bit components have multiple multi-bit cells implemented within a same component. Scannable multi-bit cells and components are similar to multi-bit cells and components but contain scannable sequential elements with scan chains installed. Multi-bit cells may or may not have each sequential cells' input and each sequential cells' output available externally. The scannable sequential elements of a multi-bit component are ordered into a predefined scan chain which is defined by the library containing the multi-bit component or multi-bit cell. During scan replacement processes of the EDA compile process, multi-bit cells and components of the netlist are replaced with scannable multi-bit cells and components. Also, during optimization, multi-bit cells and components undergo equivalence replacement to meet specified constraints (e.g., area, performance, etc.). To model the electrical characteristics of the port during certain optimizations, loopback connections are applied to the multi-bit components from the scan out port to the scan in port of the multi-bit cell or component, therefore, one loopback connection spans multiple sequential cells within the multi-bit cell or component. During certain optimizations, loopback connections are applied to multiple sequential cells that are coupled together but do not necessarily reside in a multi-bit cell or component. By spanning multiple sequential cells, circuit degeneration is reduced thereby providing better circuit optimizations for netlists having scan circuitry.
    • 一种用于电子设计自动化(EDA)的计算机实现的过程和系统,其使用具有用于建模端口电特性的环回连接的多个单元组。 多位单元具有在相同单元内实现的具有相同功能的多个门。 多位组件具有在相同组件内实现的多个多位单元。 可扫描的多位单元和组件类似于多位单元和组件,但是包含可扫描顺序元件,并安装了扫描链。 多位单元可以具有或不具有每个顺序单元的输入,并且每个顺序单元的输出可从外部获得。 多位组件的可扫描顺序元素被排序到由包含多位组件或多位单元的库定义的预定义扫描链中。 在EDA编译过程的扫描替换过程中,网表的多位单元和组件被可扫描的多位单元和组件替代。 此外,在优化期间,多位单元和组件进行等价替换以满足指定的约束(例如,面积,性能等)。 为了在某​​些优化期间对端口的电气特性进行建模,环回连接被应用于多位组件从多位单元或组件的扫描输出端口到扫描端口,因此一个环回连接跨越多个连续单元 在多位单元或组件内。 在某些优化期间,环回连接被应用于耦合在一起但不一定驻留在多位单元或组件中的多个顺序单元。 通过跨越多个顺序单元,电路退化被减少,从而为具有扫描电路的网表提供更好的电路优化。
    • 2. 发明授权
    • Pre-synthesis test point insertion
    • 预合成测试点插入
    • US06311317B1
    • 2001-10-30
    • US09282304
    • 1999-03-31
    • Ajay KhocheHarbinder SinghDhiraj GoswamiDenis Martin
    • Ajay KhocheHarbinder SinghDhiraj GoswamiDenis Martin
    • G06F1750
    • G01R31/3185G06F17/5045
    • A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.
    • 在集成电路设计中插入测试点的方法和系统。 根据本发明,在电子设计过程的早期以及在逻辑合成之前插入测试点,使得可以避免设计约束违规的问题。 本发明的一个实施例包括计算机实现的接收集成电路设计的未映射网表的步骤,以及从外部源接收指示要插入的测试点的位置和期望功能的数据。 此后,本发明在所指示的位置插入通用测试点电路,并生成修改的未映射网表。 随后,本发明对经修改的未映射网表执行逻辑合成处理,其中通用测试点电路退化为用于执行所需功能的实际测试点电路。 实际的测试点电路也可以与集成电路的其他电路合并以产生更有效的设计。
    • 3. 发明申请
    • METHOD FOR VEHICLE DRIVING ASSISTANCE
    • 车辆驾驶辅助方法
    • US20130006514A1
    • 2013-01-03
    • US13579196
    • 2011-02-25
    • Denis MartinJeremy Buisson
    • Denis MartinJeremy Buisson
    • G01C21/26
    • G01M17/02B60W30/10G01M17/06
    • The invention relates to a method for assisting in the driving of a vehicle during a braking test on said vehicle on a track, said track being divided into a plurality of adjacent strips (Z1, . . . , Zn) mainly extending lengthwise in the track, the width (Iz) of each strip being greater than or equal to the width of the tyres of the vehicle, each strip being worn on each braking of the vehicle on said strip. The assistance method comprises a step of selecting at least one strip out of the plurality of strips of the track, said strip being selected according to its level of wear. The assistance method also comprises a step of determining a theoretical trajectory of the vehicle, such that, by following said theoretical trajectory, the vehicle is able to brake on the selected strip.
    • 本发明涉及一种用于在轨道上对所述车辆进行制动测试期间辅助车辆行驶的方法,所述轨道被分成多个相邻的条带(Z1 ...,Zn),所述多个相邻条带(Z1,...,Zn)主要在轨道中纵向延伸 每个条的宽度(Iz)大于或等于车辆的轮胎宽度,每条在所述条上的车辆的每次制动上都被磨损。 辅助方法包括从轨道的多个条中选择至少一个条带的步骤,所述条带根据其磨损程度来选择。 辅助方法还包括确定车辆的理论轨迹的步骤,使得通过遵循所述理论轨迹,车辆能够在所选择的条上制动。