专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07852673B2 Method for operating nonvolatitle memory array 有权
标题翻译：用于操作非标量存储器阵列的方法
公开(公告)号：US07852673B2
公开(公告)日：2010-12-14
申请号：US12561849
申请日：2009-09-17
申请人： Hao-Ming Lien , Ming-Hsiu Lee
发明人： Hao-Ming Lien , Ming-Hsiu Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.
摘要翻译：一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

2. 发明申请

US20070291551A1 NONVOLATITLE MEMORY ARRAY AND METHOD FOR OPERATING THEREOF 审中-公开
标题翻译：非易失性存储器阵列及其操作方法
公开(公告)号：US20070291551A1
公开(公告)日：2007-12-20
申请号：US11530585
申请日：2006-09-11
申请人： Hao-Ming Lien , Ming-Hsiu Lee
发明人： Hao-Ming Lien , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.
摘要翻译：混合非易失性存储器阵列。在混合非易失性存储器阵列中，每个非易失性存储单元具有至少一个耗尽型存储单元。耗尽模式区域由栅极结构和掺杂区域组成。由于掺杂区域的厚度相对较薄，所以在栅极结构上施加电压以反转栅极结构下的掺杂区域的导电类型。同时，在掺杂区域的两个端子处施加偏压，以便控制耗尽型存储单元的工作。此外，混合非易失性存储器阵列的每个非易失性存储单元还包括增强型存储单元。因此，每个非易失性存储单元提供至少四个载波存储空间，使得存储在单元存储器件中的位数增加。

3. 发明申请

US20100008153A1 METHOD FOR OPERATING NONVOLATITLE MEMORY ARRAY 有权
标题翻译：操作非易失性存储器阵列的方法
公开(公告)号：US20100008153A1
公开(公告)日：2010-01-14
申请号：US12561849
申请日：2009-09-17
申请人： Hao-Ming Lien , Ming-Hsiu Lee
发明人： Hao-Ming Lien , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.
摘要翻译：一种用于编程具有多个混合存储器单元的混合非易失性存储器阵列的方法，其中每个混合存储单元包括耗尽型存储单元和增强型存储单元。该方法包括以通道热载波的方式对增强型存储器单元进行编程的步骤，并以带对带隧道热载波的方式对耗尽型存储单元进行编程。

4. 发明授权

US09035275B2 Three dimensional memory array adjacent to trench sidewalls 有权
标题翻译：与沟槽侧壁相邻的三维存储器阵列
公开(公告)号：US09035275B2
公开(公告)日：2015-05-19
申请号：US13330525
申请日：2011-12-19
申请人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
发明人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
IPC分类号： H01L29/06 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1633
摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
摘要翻译：一种自对准堆叠式存储单元阵列结构及其制造方法。存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

5. 发明授权

US08324605B2 Dielectric mesh isolated phase change structure for phase change memory 有权
标题翻译：介质网隔离相变结构相变记忆
公开(公告)号：US08324605B2
公开(公告)日：2012-12-04
申请号：US12286874
申请日：2008-10-02
申请人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
发明人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
摘要翻译：使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

6. 发明申请

US20110069538A1 MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE 失效
标题翻译：通过改变复位电压，PCM的多级电容编程
公开(公告)号：US20110069538A1
公开(公告)日：2011-03-24
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

7. 发明申请

US20100328996A1 PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES 有权
标题翻译：具有一个或多个不间断的配置文件的相位更改记忆
公开(公告)号：US20100328996A1
公开(公告)日：2010-12-30
申请号：US12729837
申请日：2010-03-23
申请人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
发明人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用“非恒定”浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

8. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

9. 发明申请

US20100290293A1 METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME 审中-公开
标题翻译：通过边界读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20100290293A1
公开(公告)日：2010-11-18
申请号：US12845064
申请日：2010-07-28
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

10. 发明授权

US07564710B2 Circuit for programming a memory element 有权
标题翻译：用于编程存储元件的电路
公开(公告)号：US07564710B2
公开(公告)日：2009-07-21
申请号：US11742090
申请日：2007-04-30
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00 , G11C11/56
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2213/79
摘要： An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.
摘要翻译：集成电路包括被配置为被编程为至少三个电阻状态中的任一个的存储器元件和电路。电路被配置为通过向存储元件施加脉冲将存储器元件编程为至少三个电阻状态中的所选择的一个。脉冲包括至少三个尾部中的一个，其中每个尾部对应于至少三个电阻状态中的一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式