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1. 发明申请

US20100328996A1 PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES 有权
标题翻译：具有一个或多个不间断的配置文件的相位更改记忆
公开(公告)号：US20100328996A1
公开(公告)日：2010-12-30
申请号：US12729837
申请日：2010-03-23
申请人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
发明人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用“非恒定”浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

2. 发明申请

US20110049456A1 PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY 审中-公开
标题翻译：用于相变记忆的复合掺杂相变结构
公开(公告)号：US20110049456A1
公开(公告)日：2011-03-03
申请号：US12553784
申请日：2009-09-03
申请人： HSIANG-LAN LUNG , CHIEH-FANG CHEN , YEN-HAO SHIH , HUAI-YU CHENG , ERH-KUN LAI , MING HSIU LEE , MATTHEW J. BREITWISCH , SIMONE RAO , CHUNG HON LAM
发明人： HSIANG-LAN LUNG , CHIEH-FANG CHEN , YEN-HAO SHIH , HUAI-YU CHENG , ERH-KUN LAI , MING HSIU LEE , MATTHEW J. BREITWISCH , SIMONE RAO , CHUNG HON LAM
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1641
摘要： A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region.
摘要翻译：使用在第一电极和第二电极之间的复合掺杂相变材料来描述存储器件。相变材料的存储元件，例如硫族化物，位于第一和第二电极之间并且具有有源区。相变材料具有第一掺杂剂，例如氧化硅，其特征在于倾向于在有源区域中的晶界上与相变材料分离，并且具有第二掺杂剂，例如硅，其特征在于引起再结晶温度的增加的和/或抑制活性区域中的相变材料中的空隙形成。

3. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

4. 发明申请

US20100165728A1 PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE 有权
标题翻译：在高电压状态下有两个或更多的大面积非晶区域的相变装置
公开(公告)号：US20100165728A1
公开(公告)日：2010-07-01
申请号：US12717850
申请日：2010-03-04
申请人： YEN-HAO SHIH , Chieh-Fang Chen , Hsiang-Lan Lung
发明人： YEN-HAO SHIH , Chieh-Fang Chen , Hsiang-Lan Lung
IPC分类号： G11C11/00
CPC分类号： H01L45/126 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.
摘要翻译：这里描述了存储器件以及用于操作存储器件的方法。如本文所述的存储单元包括第一电极和第二电极。存储单元还包括具有沿第一和第二电极之间的电极间电流路径串联布置的第一和第二有源区的相变材料。

5. 发明申请

US20120231613A1 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE 有权
标题翻译： 3D内存阵列安排FN隧道程序和删除
公开(公告)号：US20120231613A1
公开(公告)日：2012-09-13
申请号：US13476964
申请日：2012-05-21
申请人： HSIANG-LAN LUNG , YEN-HAO SHIH , ERH-KUN LAI , MING HSIU LEE , HANG-TING LUE
发明人： HSIANG-LAN LUNG , YEN-HAO SHIH , ERH-KUN LAI , MING HSIU LEE , HANG-TING LUE
IPC分类号： H01L21/20
CPC分类号： G11C16/0458 , H01L27/0688 , H01L27/10 , H01L27/11578 , H01L27/11582
摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。该设备可以作为3D和解码的闪存操作。

6. 发明申请

US20140119127A1 DIELECTRIC CHARGE TRAPPING MEMORY CELLS WITH REDUNDANCY 有权
标题翻译：具有冗余性的电介质电荷捕获记忆细胞
公开(公告)号：US20140119127A1
公开(公告)日：2014-05-01
申请号：US13661723
申请日：2012-10-26
申请人： Hsiang-Lan Lung , YEN-HAO SHIH , ERH-KUN LAI , MING-HSIU LEE
发明人： Hsiang-Lan Lung , YEN-HAO SHIH , ERH-KUN LAI , MING-HSIU LEE
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C16/10
摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
摘要翻译：介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

7. 发明申请

US20100177553A1 REWRITABLE MEMORY DEVICE 有权
标题翻译：可恢复存储器件
公开(公告)号：US20100177553A1
公开(公告)日：2010-07-15
申请号：US12488795
申请日：2009-06-22
申请人： MING-HSIU LEE , CHIEH-FANG CHEN , YEN-HAO SHIH , YU ZHU
发明人： MING-HSIU LEE , CHIEH-FANG CHEN , YEN-HAO SHIH , YU ZHU
IPC分类号： G11C11/00 , H01L47/00 , G11C11/34
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/33 , G11C2213/79 , H01L45/08 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.
摘要翻译：通过将电绝缘层从存储材料中物理分离出来以建立高电阻状态，并且通过将电绝缘层的至少一部分再吸收到存储材料中以建立低电阻状态。编程和擦除的物理机制包括结构空位的移动以形成空隙，和/或掺杂材料和体材料的偏析，以产生由空隙和/或介电掺杂材料构成的电绝缘层，沿着电极间电流通路电极。

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