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1. 发明授权

US08176110B2 Modular multiplier 有权
标题翻译：模数乘法器
公开(公告)号：US08176110B2
公开(公告)日：2012-05-08
申请号：US12256295
申请日：2008-10-22
申请人： Hans Eberle , Nils Gura , Russell A. Brown , Sheueling Chang-Shantz , Vipul Gupta
发明人： Hans Eberle , Nils Gura , Russell A. Brown , Sheueling Chang-Shantz , Vipul Gupta
IPC分类号： G06F7/38 , H04L9/00
CPC分类号： G06F7/724 , G06F7/527 , G06F7/725
摘要： Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.
摘要翻译：在GF（2）上的两个元素X（t）和Y（t）的模数乘法，其中m是场度，可以利用场度至少部分地确定迭代次数。当迭代次数减少时，可以采用额外的移位操作。在GF（2）上的两个元件X（t）和Y（t）的模块化乘法可以包括在乘法和还原期间使用的共享减少电路。此外，在GF（2）上的二进制多项式X（t）和Y（t）的模乘可以利用Karatsuba算法，例如通过将乘法递归地分解成根据Karatsuba算法确定的较小操作数。

2. 发明授权

US07461115B2 Modular multiplier 有权
标题翻译：模数乘法器
公开(公告)号：US07461115B2
公开(公告)日：2008-12-02
申请号：US10387009
申请日：2003-03-11
申请人： Hans Eberle , Nils Gura , Russell A. Brown , Sheueling Chang-Shantz , Vipul Gupta
发明人： Hans Eberle , Nils Gura , Russell A. Brown , Sheueling Chang-Shantz , Vipul Gupta
IPC分类号： G06F7/00 , H04L9/00
CPC分类号： G06F7/724 , G06F7/527 , G06F7/725
摘要： Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.
摘要翻译：在GF（2）上的两个元素X（t）和Y（t）的模数乘法，其中m是场度，可以利用场度至少部分地确定迭代次数。当迭代次数减少时，可以采用额外的移位操作。在GF（2）上的两个元件X（t）和Y（t）的模块化乘法可以包括在乘法和还原期间使用的共享减少电路。此外，在GF（2）上的二进制多项式X（t）和Y（t）的模乘可以利用Karatsuba算法，例如通过将乘法递归地分解成根据Karatsuba算法确定的较小操作数。

3. 发明申请

US20090067619A1 Modular Multiplier 有权
标题翻译：模块化乘数
公开(公告)号：US20090067619A1
公开(公告)日：2009-03-12
申请号：US12256295
申请日：2008-10-22
申请人： Hans Eberle , Nils Gura , Russell A. Brown , Sheueling Chang-Shantz , Vipul Gupta
发明人： Hans Eberle , Nils Gura , Russell A. Brown , Sheueling Chang-Shantz , Vipul Gupta
IPC分类号： H04L9/28
CPC分类号： G06F7/724 , G06F7/527 , G06F7/725
摘要： Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.
摘要翻译：在GF（2）上的两个元素X（t）和Y（t）的模数乘法，其中m是场度，可以利用场度至少部分地确定迭代次数。当迭代次数减少时，可以采用额外的移位操作。在GF（2）上的两个元件X（t）和Y（t）的模块化乘法可以包括在乘法和还原期间使用的共享减少电路。此外，在GF（2）上的二进制多项式X（t）和Y（t）的模乘可以利用Karatsuba算法，例如通过将乘法递归地分解成根据Karatsuba算法确定的较小操作数。

4. 发明授权

US07508936B2 Hardware accelerator for elliptic curve cryptography 有权
标题翻译：椭圆曲线加密的硬件加速器
公开(公告)号：US07508936B2
公开(公告)日：2009-03-24
申请号：US10387007
申请日：2003-03-11
申请人： Hans Eberle , Nils Gura , Daniel Finchelstein , Sheueling Chang-Shantz , Vipul Gupta
发明人： Hans Eberle , Nils Gura , Daniel Finchelstein , Sheueling Chang-Shantz , Vipul Gupta
IPC分类号： H04L9/00 , H04L9/32 , H04L9/30 , H04L9/28 , G06F1/02 , G06F7/38
CPC分类号： G06F7/724 , G06F7/527 , G06F7/725
摘要： An elliptic curve processing apparatus that performs operations on elliptic curves specified over binary polynomial fields includes a functional unit that has a digit serial multiplier with a digit size of at least two bits. The elliptic curve processing apparatus performs reduction for respective generic curves using arbitrary irreducible polynomials, which correspond to respective ones of the generic curves. The elliptic curve processing apparatus may include hardwired reduction circuits in the functional unit for use with respective named curves. A storage location in the elliptic curve processing apparatus may be used to specify whether an operation is for one of the named curves or for one of the generic curves. The elliptic curve processing apparatus responds to an arithmetic instruction to utilize a respective one of the hardwired reduction circuits for reduction for respective named curves and a multiplier circuit for reduction for a plurality of generic curves, the multiplier coupled to perform reduction for respective generic curves using arbitrary irreducible polynomials, the arbitrary irreducible polynomials corresponding to respective ones of the generic curves. The elliptic curve processing apparatus operable on elliptic curves specified over binary polynomial fields performs a conditional branch according to whether a curve being processed is a generic curve or a named curve.
摘要翻译：对二进制多项式场指定的椭圆曲线进行运算的椭圆曲线处理装置包括功能单元，其具有位数至少为2位的数字串行乘法器。椭圆曲线处理装置使用对应于各个通用曲线的任意不可约多项式来对各个通用曲线进行缩减。椭圆曲线处理装置可以包括用于与各自命名的曲线一起使用的功能单元中的硬连线减少电路。可以使用椭圆曲线处理装置中的存储位置来指定操作是针对一个命名曲线还是针对一个通用曲线。椭圆曲线处理装置响应算术指令以利用硬连线减少电路中的相应一个用于相应命名曲线的减少，以及用于多个通用曲线的减少的乘法器电路，该乘法器耦合以对各个通用曲线进行减少，使用任意的不可约多项式，对应于各个通用曲线的任意不可约多项式。根据二进制多项式场指定的椭圆曲线可操作的椭圆曲线处理装置根据正在处理的曲线是通用曲线还是命名曲线来执行条件分支。

5. 发明授权

US08213606B2 Method and apparatus for implementing processor instructions for accelerating public-key cryptography 有权
标题翻译：用于实现用于加速公钥密码术的处理器指令的方法和装置
公开(公告)号：US08213606B2
公开(公告)日：2012-07-03
申请号：US10789311
申请日：2004-02-27
申请人： Sheueling Chang Shantz , Leonard Rarick , Lawrence Spracklen , Hans Eberle , Nils Gura
发明人： Sheueling Chang Shantz , Leonard Rarick , Lawrence Spracklen , Hans Eberle , Nils Gura
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/5318 , G06F7/5443 , G06F9/3001 , G06F9/30094 , G06F9/30101 , G06F9/3851
摘要： In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.
摘要翻译：响应于执行算术指令，将第一数乘以第二数，并且从先前执行的单个算术指令的部分结果从当前算术指令的高阶位产生的第一进位保存加法器结构反馈给第二进位保存加法器树结构用于生成当前算术指令的低位比特，以生成表示与先前执行的算术指令相加的与高位相加的第二数的第一数字的结果。可以执行算术指令可以产生表示第一数乘以与部分结果相加的第二数的结果，并且还与第三数相加，第三数被馈送到进位保存加法器树结构。

6. 发明授权

US08194855B2 Method and apparatus for implementing processor instructions for accelerating public-key cryptography 有权
标题翻译：用于实现用于加速公钥密码术的处理器指令的方法和装置
公开(公告)号：US08194855B2
公开(公告)日：2012-06-05
申请号：US10626420
申请日：2003-07-24
申请人： Sheueling Chang Shantz , Hans Eberle , Nils Gura , Lawrence Spracklen , Leonard Rarick
发明人： Sheueling Chang Shantz , Hans Eberle , Nils Gura , Lawrence Spracklen , Leonard Rarick
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/5318 , G06F7/5443 , G06F9/3001 , G06F9/30094 , G06F9/30101 , G06F9/3851
摘要： In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.
摘要翻译：响应于执行单个算术指令，将第一数乘以第二数，并且隐式地添加来自先前执行的单个算术指令的部分结果，以生成表示第一数乘以与第二数相乘的第二数的结果来自先前执行的单个算术指令的部分结果。生成结果的高阶部分作为下一个部分结果保存在扩展进位寄存器中，用于执行后续的单个算术指令。可以执行单个算术指令来产生表示第一个数乘以与部分结果相加的第二个数字并且与第三个数字相加的结果。

7. 发明授权

US08532102B2 Simple fairness protocols for daisy chain interconnects 有权
公开(公告)号：US08532102B2
公开(公告)日：2013-09-10
申请号：US13414629
申请日：2012-03-07
申请人： Wladyslaw Olesinski , Hans Eberle , Nils Gura , Robert A. Dickson , Aron J. Silverton , Sumti Jairath , Peter J. Yakutis
发明人： Wladyslaw Olesinski , Hans Eberle , Nils Gura , Robert A. Dickson , Aron J. Silverton , Sumti Jairath , Peter J. Yakutis
IPC分类号： H04L12/26
CPC分类号： H04L47/10
摘要： A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

8. 发明授权

US08145823B2 Parallel wrapped wave-front arbiter 有权
标题翻译：平行缠绕的波前仲裁器
公开(公告)号：US08145823B2
公开(公告)日：2012-03-27
申请号：US11731590
申请日：2007-03-29
申请人： Wladyslaw Olesinski , Hans Eberle , Nils Gura
发明人： Wladyslaw Olesinski , Hans Eberle , Nils Gura
IPC分类号： G06F13/00
CPC分类号： H04L12/5601 , H04L49/1553 , H04L49/3045 , H04L2012/5605 , H04L2012/5679 , H04L2012/5681
摘要： Embodiments of the present invention provide a system that schedules the transfer of cells in a switch. The system starts by receiving a set of cells to be transferred from a set of inputs of the switch to a set of outputs of the switch. The system includes S subschedulers, wherein each subscheduler processes N scheduling waves in sequence to generate a conflict-free transfer schedule for a given time slot for a matrix of transfer elements in the switch. The system then operates the subschedulers in parallel to generate S transfer schedules to transfer the cells from the set of inputs of the switch to the set of outputs of the switch during S time slots.
摘要翻译：本发明的实施例提供一种调度交换机中的小区的传输的系统。系统通过接收要从交换机的一组输入传送到交换机的一组输出的一组单元开始。该系统包括S个调度器，其中每个调度器按顺序处理N个调度波，以为交换机中的传送单元矩阵的给定时隙生成无冲突传输调度。然后，该系统并行地操作调度器以产生S个传输调度，以在S个时隙期间将单元从该组开关的输入传送到该组开关的一组输出。

9. 发明授权

US07925816B2 Architecture for an output buffered switch with input groups 有权
标题翻译：具有输入组的输出缓冲交换机的架构
公开(公告)号：US07925816B2
公开(公告)日：2011-04-12
申请号：US11731672
申请日：2007-03-30
申请人： Wladyslaw Olesinski , Hans Eberle , Nils Gura
发明人： Wladyslaw Olesinski , Hans Eberle , Nils Gura
IPC分类号： G06F13/00 , G06F13/38
CPC分类号： G06F13/4022
摘要： Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips.
摘要翻译：本发明的实施例提供一种通过交换机在计算机系统中的组件之间传送数据的系统。在这些实施例中，开关包括耦合在一起并被配置为共同用作开关的多个开关芯片。在操作期间，每个开关芯片从该组输入的子集接收单元，并且选择性地将每个单元传输到耦合到开关芯片或该组的子集的该组输出的子集的至少一个输出耦合到其他开关芯片的输出。

10. 发明授权

US07912068B2 Low-latency scheduling in large switches 有权
标题翻译：大型交换机中的低延迟调度
公开(公告)号：US07912068B2
公开(公告)日：2011-03-22
申请号：US12135467
申请日：2008-06-09
申请人： Hans Eberle , Nils Gura , Wladyslaw Olesinski , Andreas Mejia
发明人： Hans Eberle , Nils Gura , Wladyslaw Olesinski , Andreas Mejia
IPC分类号： H04L12/28
CPC分类号： H04L49/254 , H04L47/50 , H04L47/6255 , H04L49/3045
摘要： Embodiments of a scheduler for a switch, where the switch is configured to couple input ports to output ports are described. During operation, the scheduler may determine a schedule based on a group of requests, associated with multiple data streams, that are received for the output ports of the switch, where the schedule matches input ports to output ports of the switch for a given data cell time. Note that the schedule may be determined using an arbitration technique during a time interval. Moreover, the scheduler may assign an additional request, which was received at a time that precedes a current time by less than the time interval, to a portion of the switch which is available in the schedule, thereby reducing a latency of the scheduler.
摘要翻译：描述了用于交换机的调度器的实施例，其中交换机被配置为将输入端口耦合到输出端口。在操作期间，调度器可以基于与多个数据流相关联的一组请求来确定与该交换机的输出端口接收的一组请求，其中该调度将输入端口与给定数据单元的交换机的输出端口匹配时间。注意，可以在时间间隔期间使用仲裁技术来确定调度。此外，调度器可以将在当前时间之前的时间小于时间间隔的时间分配附加到在调度中可用的交换机的一部分，从而减少调度器的等待时间。

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