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1. 发明授权

US08213606B2 Method and apparatus for implementing processor instructions for accelerating public-key cryptography 有权
标题翻译：用于实现用于加速公钥密码术的处理器指令的方法和装置
公开(公告)号：US08213606B2
公开(公告)日：2012-07-03
申请号：US10789311
申请日：2004-02-27
申请人： Sheueling Chang Shantz , Leonard Rarick , Lawrence Spracklen , Hans Eberle , Nils Gura
发明人： Sheueling Chang Shantz , Leonard Rarick , Lawrence Spracklen , Hans Eberle , Nils Gura
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/5318 , G06F7/5443 , G06F9/3001 , G06F9/30094 , G06F9/30101 , G06F9/3851
摘要： In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.
摘要翻译：响应于执行算术指令，将第一数乘以第二数，并且从先前执行的单个算术指令的部分结果从当前算术指令的高阶位产生的第一进位保存加法器结构反馈给第二进位保存加法器树结构用于生成当前算术指令的低位比特，以生成表示与先前执行的算术指令相加的与高位相加的第二数的第一数字的结果。可以执行算术指令可以产生表示第一数乘以与部分结果相加的第二数的结果，并且还与第三数相加，第三数被馈送到进位保存加法器树结构。

2. 发明授权

US08194855B2 Method and apparatus for implementing processor instructions for accelerating public-key cryptography 有权
标题翻译：用于实现用于加速公钥密码术的处理器指令的方法和装置
公开(公告)号：US08194855B2
公开(公告)日：2012-06-05
申请号：US10626420
申请日：2003-07-24
申请人： Sheueling Chang Shantz , Hans Eberle , Nils Gura , Lawrence Spracklen , Leonard Rarick
发明人： Sheueling Chang Shantz , Hans Eberle , Nils Gura , Lawrence Spracklen , Leonard Rarick
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/5318 , G06F7/5443 , G06F9/3001 , G06F9/30094 , G06F9/30101 , G06F9/3851
摘要： In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.
摘要翻译：响应于执行单个算术指令，将第一数乘以第二数，并且隐式地添加来自先前执行的单个算术指令的部分结果，以生成表示第一数乘以与第二数相乘的第二数的结果来自先前执行的单个算术指令的部分结果。生成结果的高阶部分作为下一个部分结果保存在扩展进位寄存器中，用于执行后续的单个算术指令。可以执行单个算术指令来产生表示第一个数乘以与部分结果相加的第二个数字并且与第三个数字相加的结果。

3. 发明申请

US20070143389A1 Efficient error-check and exact-check for newton-raphson divide and square-root operations 有权
标题翻译：对牛顿 - 拉夫逊分割和平方根操作进行有效的错误检查和精确检查
公开(公告)号：US20070143389A1
公开(公告)日：2007-06-21
申请号：US11314639
申请日：2005-12-20
申请人： Allen Lyu , Leonard Rarick
发明人： Allen Lyu , Leonard Rarick
IPC分类号： G06F7/38
CPC分类号： G06F7/552 , G06F7/49947 , G06F7/535 , G06F2207/5355
摘要： One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a divide or a square-root operation to produce a result, which includes one or more additional bits of accuracy beyond a desired accuracy for the result. Next, the system rounds the result to the desired accuracy to produce a rounded result t. The system then analyzes the additional bits of accuracy to determine whether t is correct and whether t is exact.
摘要翻译：本发明的一个实施例提供了一种执行牛顿 - 拉夫逊分割或平方根计算的误检和精确检查操作的系统。在操作期间，系统执行牛顿 - 拉夫逊迭代，然后进行乘法除法或平方根操作，以产生结果，其中包括一个或多个精度超过所需精度的附加位。接下来，系统将结果舍入到期望的精度以产生舍入结果t。然后，系统分析精度的附加位，以确定t是否正确以及t是否精确。

4. 发明授权

US06581079B2 Apparatus for computing transcendental functions quickly 有权
标题翻译：用于快速计算超验功能的装置
公开(公告)号：US06581079B2
公开(公告)日：2003-06-17
申请号：US10012660
申请日：2001-11-12
申请人： Leonard Rarick
发明人： Leonard Rarick
IPC分类号： G06F738
CPC分类号： G06F7/556 , G06F7/548
摘要： The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.
摘要翻译：本发明提供了一种快速计算超越函数的方法和系统：（1）增加乘法ALU以向产品添加项，（2）跳过中间乘数的舍入运算，（3）泰勒级数分为并行执行两个部分系列。因此，在十个时钟内执行具有十个术语（例如，SIN或COS）的超验功能。

5. 发明申请

US20050010527A1 Method and apparatus for fast RC4-like encryption 有权
标题翻译：快速RC4类加密的方法和装置
公开(公告)号：US20050010527A1
公开(公告)日：2005-01-13
申请号：US10617632
申请日：2003-07-11
申请人： Leonard Rarick , Christopher Olson
发明人： Leonard Rarick , Christopher Olson
IPC分类号： H04L9/18 , G06F17/60
CPC分类号： H04L9/065 , H04L2209/125
摘要： A method and apparatus for encrypting information. In one embodiment, a method for encrypting information includes obtaining a value A from an array having a plurality of values and determining a value B based on the value A in a first pipeline stage. In a second pipeline stage, a value V may be determined from the value A and the value B. The value V may then be exclusive ORed (XORed) with a data value that forms a portion of the information being encrypted. A first logic unit may include the first pipeline stage, while a second logic unit may include the second pipeline stage. The array may be stored in a plurality of flip-flops in one embodiment, or may be stored in one or more register files in a second embodiment. The method and apparatus may be used for decrypting information as well.
摘要翻译：一种用于加密信息的方法和装置。在一个实施例中，用于加密信息的方法包括从具有多个值的阵列中获得值A，并且基于第一流水线级中的值A来确定值B. 在第二流水线阶段，可以从值A和值B确定值V.然后，值V可以与形成被加密的信息的一部分的数据值异或（异或）。第一逻辑单元可以包括第一流水线级，而第二逻辑单元可以包括第二流水线级。在一个实施例中，阵列可以存储在多个触发器中，或者可以在第二实施例中存储在一个或多个寄存器文件中。该方法和装置也可用于解密信息。

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