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1. 发明授权

US08611162B2 Circuit for preventing a dummy read in a memory 有权
标题翻译：用于防止在存储器中进行虚拟读取的电路
公开(公告)号：US08611162B2
公开(公告)日：2013-12-17
申请号：US13075768
申请日：2011-03-30
申请人： Hamed Ghassemi , Jogendra C. Sarker
发明人： Hamed Ghassemi , Jogendra C. Sarker
IPC分类号： G11C7/22
CPC分类号： G11C11/412 , G11C11/419
摘要： A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal.
摘要翻译：存储器包括行解码器，列逻辑和具有以行和列排列的多个存储器单元的存储器阵列。多个写入字线耦合到行解码器。多个互补写入字线耦合到行解码器。多个读位线耦合到列逻辑。多个写位线耦合到列逻辑。多个列解码写使能线耦合到列逻辑。多个存储单元中的每个存储单元耦合到相应的写入控制电路。每个写入控制电路包括耦合在列解码写入使能线和存储器单元的存取晶体管之间的传输门。传输门由写入字线信号控制。

2. 发明授权

US09021194B2 Memory management unit tag memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US09021194B2
公开(公告)日：2015-04-28
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F9/355 , G06F9/38 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

3. 发明申请

US20130046928A1 Memory Management Unit Tag Memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

4. 发明申请

US20100312957A1 TRANSLATION LOOK-ASIDE BUFFER WITH A TAG MEMORY AND METHOD THEREFOR 有权
标题翻译：翻译带有标记内存的缓冲区及其方法
公开(公告)号：US20100312957A1
公开(公告)日：2010-12-09
申请号：US12480809
申请日：2009-06-09
申请人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
发明人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
IPC分类号： G06F12/00 , G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0895
摘要： A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage portion that is constructed as a CAM. For each row of the CAM a match determination is made that indicates if the TAG portion is the same as contents of the particular row. A decoder decodes an index portion and provides an output for each row. On a per row basis the output of the decoder is logically combined with the hit/miss signals to determine if there is a hit for the TAG memory. If there is a hit for the TAG memory, a translated address corresponding to the index portion of the address is then output as the selected translated address.
摘要翻译：翻译后备缓冲器（TLB）具有用于确定所需翻译地址是否存储在TLB中的TAG存储器。将TAG部分与TAG存储器的内容进行比较，而不需要读取TAG存储器，因为TAG存储器具有构造为CAM的存储部分。对于CAM的每一行，进行匹配确定，其指示TAG部分是否与特定行的内容相同。解码器解码索引部分并为每行提供输出。在每行的基础上，解码器的输出与命中/未命中信号逻辑地组合以确定是否存在对TAG存储器的命中。如果存在TAG存储器的命中，则将与地址的索引部分相对应的翻译地址作为选择的翻译地址输出。

5. 发明授权

US08099580B2 Translation look-aside buffer with a tag memory and method therefor 有权
标题翻译：具有标签记忆的翻译后备缓冲器及其方法
公开(公告)号：US08099580B2
公开(公告)日：2012-01-17
申请号：US12480809
申请日：2009-06-09
申请人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
发明人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0895
摘要： A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage portion that is constructed as a CAM. For each row of the CAM a match determination is made that indicates if the TAG portion is the same as contents of the particular row. A decoder decodes an index portion and provides an output for each row. On a per row basis the output of the decoder is logically combined with the hit/miss signals to determine if there is a hit for the TAG memory. If there is a hit for the TAG memory, a translated address corresponding to the index portion of the address is then output as the selected translated address.
摘要翻译：翻译后备缓冲器（TLB）具有用于确定所需翻译地址是否存储在TLB中的TAG存储器。将TAG部分与TAG存储器的内容进行比较，而不需要读取TAG存储器，因为TAG存储器具有构造为CAM的存储部分。对于CAM的每一行，进行匹配确定，其指示TAG部分是否与特定行的内容相同。解码器解码索引部分并为每行提供输出。在每行的基础上，解码器的输出与命中/未命中信号逻辑地组合以确定是否存在对TAG存储器的命中。如果存在TAG存储器的命中，则将与地址的索引部分相对应的翻译地址作为选择的翻译地址输出。

6. 发明申请

US20080109508A1 SYSTEM HAVING A CARRY LOOK-AHEAD (CLA) ADDER 审中-公开
标题翻译：系统有一个携带的前瞻性（CLA）ADDER
公开(公告)号：US20080109508A1
公开(公告)日：2008-05-08
申请号：US11550835
申请日：2006-10-19
申请人： Prashant U. Kenkare , Jogendra C. Sarker
发明人： Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： In a system having stored operands in various locations, addition is performed without having to store the operands in preparation for an add operation. Bitwise propagate and generate terms are efficiently created to speed up additions in the system. Combinational logic circuitry has a plurality of inputs and provides a first operand and a second operand during a first phase of a cycle of a clock signal. A carry look-ahead adder (CLA) has first and second inputs directly connected to the combinational logic circuitry for respectively receiving the first operand and the second operand during the first phase of the cycle of the clock signal and creates generate bits and propagate bits prior to beginning of a second phase of the cycle of the clock signal. The adder uses the generate bits and propagate bits to provide a sum of the first operand and the second operand.
摘要翻译：在具有各种位置的存储操作数的系统中，执行相加操作，而不必存储操作数以准备添加操作。有效创建按位传播和生成术语以加速系统中的添加。组合逻辑电路具有多个输入，并且在时钟信号的周期的第一阶段期间提供第一操作数和第二操作数。进位预读加法器（CLA）具有直接连接到组合逻辑电路的第一和第二输入，用于在时钟信号的周期的第一阶段期间分别接收第一操作数和第二操作数，并创建生成位和传播位到时钟信号的周期的第二阶段的开始。加法器使用生成位和传播位来提供第一操作数和第二操作数的和。

7. 发明申请

US20130238875A1 MULTIPLE PAGE SIZE MEMORY MANAGEMENT UNIT 有权
标题翻译：多页大小内存管理单元
公开(公告)号：US20130238875A1
公开(公告)日：2013-09-12
申请号：US13415196
申请日：2012-03-08
申请人： Ravindraraj Ramaraju , Eric V. Fiene , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , Eric V. Fiene , Jogendra C. Sarker
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.
摘要翻译：存储器管理单元可以接收与MMU未知的页面大小相关联的地址。 MMU可以同时确定翻译后备缓冲器数据阵列是否基于地址的不同部分存储与地址相关联的物理地址，其中每个不同部分与不同的可能的页面大小相关联。当在数据处理装置中同时执行使用不同页面大小的不同程序时，这提供了有效的翻译后备缓冲器数据阵列访问。

8. 发明授权

US07193924B2 Dual-port static random access memory having improved cell stability and write margin 有权
标题翻译：双端口静态随机存取存储器具有改善的单元稳定性和写裕度
公开(公告)号：US07193924B2
公开(公告)日：2007-03-20
申请号：US11123514
申请日：2005-05-06
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C8/16 , G11C11/412 , G11C11/413
摘要： A dual-port memory includes a plurality of memory cells coupled to a row decoder and column logic. Each memory cell includes two storage nodes, where each storage node is coupled to a bit line via an access transistor. Each memory cell also includes a logic gate for logically combining a word line signal with a column address signal and providing the resulting output signal to the gates of the access transistors. In one embodiment, the logic gate is a NOR logic gate and in another embodiment, the logic gate is a transmission gate. This prevents a potential read disturb problem with unselected memory cells of a row. This also reduces power consumption in the memory.
摘要翻译：双端口存储器包括耦合到行解码器和列逻辑的多个存储器单元。每个存储单元包括两个存储节点，其中每个存储节点经由存取晶体管耦合到位线。每个存储单元还包括用于逻辑地组合字线信号和列地址信号的逻辑门，并将得到的输出信号提供给存取晶体管的栅极。在一个实施例中，逻辑门是NOR逻辑门，在另一个实施例中，逻辑门是传输门。这可以防止一行的未选择的存储单元发生潜在的读取干扰问题。这也降低了内存中的功耗。

9. 发明授权

US09323691B2 Multiple page size memory management unit 有权
标题翻译：多页大小的内存管理单元
公开(公告)号：US09323691B2
公开(公告)日：2016-04-26
申请号：US13415196
申请日：2012-03-08
申请人： Ravindraraj Ramaraju , Eric V. Fiene , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , Eric V. Fiene , Jogendra C. Sarker
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.
摘要翻译：存储器管理单元可以接收与MMU未知的页面大小相关联的地址。 MMU可以同时确定翻译后备缓冲器数据阵列是否基于地址的不同部分存储与地址相关联的物理地址，其中每个不同部分与不同的可能的页面大小相关联。当在数据处理装置中同时执行使用不同页面大小的不同程序时，这提供了有效的翻译后备缓冲器数据阵列访问。

10. 发明授权

US07161827B2 SRAM having improved cell stability and method therefor 有权
标题翻译：具有改善细胞稳定性的SRAM及其方法
公开(公告)号：US07161827B2
公开(公告)日：2007-01-09
申请号：US11033934
申请日：2005-01-12
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A SRAM (14) includes a SRAM cell (26), the cell (26) includes a first storage node (N1), a second storage node (N2), and a cross coupled latch (40) including a first primary source current path to the first storage node, a first primary sink current path to the first storage node, a second primary source current path to the second storage node, a second primary sink current path to the second storage node, a fifth primary current path to the first storage node, and a sixth primary current path to the second storage node. During standby and/or a read operation of the SRAM cell (26), one of the fifth primary current path and the sixth primary current path is conductive. During a write operation, the fifth primary current path and the sixth primary current path are non-conductive.
摘要翻译： SRAM（14）包括SRAM单元（26），单元（26）包括第一存储节点（N 1），第二存储节点（N 2）和交叉耦合的锁存器（40），其包括第一主源到第一存储节点的当前路径，到第一存储节点的第一主宿当前路径，到第二存储节点的第二主源电流路径，到第二存储节点的第二主宿宿电流路径，第五主要电流路径第一存储节点和到第二存储节点的第六主要电流路径。在SRAM单元（26）的待机和/或读取操作期间，第五初级电流路径和第六初级电流路径之一是导电的。在写入操作期间，第五初级电流路径和第六初级电流路径是非导通的。

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