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1. 发明授权

US07346872B2 Functional timing analysis for characterization of virtual component blocks 有权
标题翻译：用于表征虚拟组件块的功能时序分析
公开(公告)号：US07346872B2
公开(公告)日：2008-03-18
申请号：US10255119
申请日：2002-09-24
申请人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
发明人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are “close” (i.e., within a specified tolerance) may be combined into a single table or matrix.
摘要翻译：提供了一种用于对虚拟组件块或其他电路模型执行定时分析的系统和方法，其中使用从电路的控制输入获得的功能信息及其有用的组合来提高精度。识别电路块的控制输入和数据输入。每个功能有意义或有用的控制输入组合被应用于电路块，并且数据输入的拓扑延迟仅沿着未被控制输入阻塞的路径确定。沿阻塞路径的延迟被忽略。通过确定源自控制输入的所有路径的拓扑延迟，而不考虑路径阻塞，进一步增加了分析，以减少可能低估数据输入延迟的可能性。最终定时模型可以包括沿着控制输入的每个组合沿着数据路径的最大延迟的组合，以及沿着源自每个控制输入的路径的最大延迟。延迟分析可以考虑不同的输入压摆和负载电容，结果可以以表格或矩阵形式表示。还提供了一种用于缩短时间延迟信息（无论是标量还是表格形式）的有用技术，以简化虚拟组件块或电路模型的时序表征。 “关闭”（即，在指定的公差内）的延迟表或矩阵可以被组合成单个表或矩阵。

2. 发明授权

US06457159B1 Functional timing analysis for characterization of virtual component blocks 有权
标题翻译：用于表征虚拟组件块的功能时序分析
公开(公告)号：US06457159B1
公开(公告)日：2002-09-24
申请号：US09477710
申请日：1999-12-28
申请人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
发明人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are “close” (i.e., within a specified tolerance) may be combined into a single table or matrix.
摘要翻译：提供了一种用于对虚拟组件块或其他电路模型执行定时分析的系统和方法，其中使用从电路的控制输入获得的功能信息及其有用的组合来提高精度。识别电路块的控制输入和数据输入。每个功能有意义或有用的控制输入组合被应用于电路块，并且数据输入的拓扑延迟仅沿着未被控制输入阻塞的路径确定。沿阻塞路径的延迟被忽略。通过确定源自控制输入的所有路径的拓扑延迟，而不考虑路径阻塞，进一步增加了分析，以减少可能低估数据输入延迟的可能性。最终定时模型可以包括沿着控制输入的每个组合沿着数据路径的最大延迟的组合，以及沿着源自每个控制输入的路径的最大延迟。延迟分析可以考虑不同的输入压摆和负载电容，结果可以以表格或矩阵形式表示。还提供了一种用于缩短时间延迟信息（无论是标量还是表格形式）的有用技术，以简化虚拟组件块或电路模型的时序表征。 “关闭”（即，在指定的公差内）的延迟表或矩阵可以组合成单个表或矩阵。

3. 发明申请

US20090115995A1 Method and system for fast calibration of three-dimensional (3D) sensors 有权
标题翻译：三维（3D）传感器快速校准的方法和系统
公开(公告)号：US20090115995A1
公开(公告)日：2009-05-07
申请号：US12319086
申请日：2008-12-30
申请人： Cyrus Bamji , Hakan Yalcin
发明人： Cyrus Bamji , Hakan Yalcin
IPC分类号： G01C5/00
CPC分类号： G01C3/08 , G01C25/00 , G01S7/497 , G01S17/36 , G01S17/89
摘要： Rapid calibration of a TOF system uses a stationary target object and electrically introduces phase shift into the TOF system to emulate target object relocation. Relatively few parameters suffice to model a parameterized mathematical representation of the transfer function between measured phase and Z distance. The phase-vs-distance model is directly evaluated during actual run-time operation of the TOF system. Preferably modeling includes two components: electrical modeling of phase-vs-distance characteristics that depend upon electrical rather than geometric characteristics of the sensing system, and elliptical modeling that phase-vs-distance characteristics that depending upon geometric rather than electrical characteristics of the sensing system.
摘要翻译： TOF系统的快速校准使用固定的目标物体，并将相移电相引入到TOF系统中以模拟目标物体重定位。相对较少的参数足以对测量相位和Z距离之间的传递函数进行参数化数学表示。在TOF系统的实际运行时间期间直接评估相位对距离模型。建模模型最好包括两个部分：取决于传感系统的电而不是几何特性的相位 - 距离特性的电气建模，以及取决于传感系统的几何而不是电特性的相位 - 距离特性的椭圆建模。

4. 发明授权

US07352454B2 Methods and devices for improved charge management for three-dimensional and color sensing 有权
标题翻译：改进三维和彩色感应电荷管理的方法和装置
公开(公告)号：US07352454B2
公开(公告)日：2008-04-01
申请号：US11349017
申请日：2006-02-06
申请人： Cyrus Bamji , Hakan Yalcin
发明人： Cyrus Bamji , Hakan Yalcin
IPC分类号： G01B11/26 , G01C1/00 , G01C3/08
CPC分类号： G01S17/89 , G01J3/50 , G01S7/4816 , G01S17/08 , G01S17/36 , H01L27/0805
摘要： TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X-dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably a potential barrier is implanted between adjacent gates and a bias gate is formed intermediate a gate and associated source region. Resultant detector structures can be operated at the more extreme gate voltages that are desirable for high performance.
摘要翻译： TOF和颜色感测检测器结构具有x轴间隔开的y轴延伸的具有相邻源收集区域的指状栅极结构。 X维结构小于y维结构并且控制性能，其特征在于高x轴电场和快速电荷运动，与较低的y轴电场和较慢的电荷运动形成对比。优选地，在相邻栅极之间注入势垒，并且在栅极和相关源极区之间形成偏压栅极。所产生的检测器结构可以在高性能所需的更极端的栅极电压下工作。

5. 发明申请

US20060128087A1 Methods and devices for improved charge management for three-dimensional and color sensing 有权
标题翻译：改进三维和彩色感应电荷管理的方法和装置
公开(公告)号：US20060128087A1
公开(公告)日：2006-06-15
申请号：US11349017
申请日：2006-02-06
申请人： Cyrus Bamji , Hakan Yalcin
发明人： Cyrus Bamji , Hakan Yalcin
IPC分类号： H01L21/8238 , G01C3/08 , H01L27/10
CPC分类号： G01S17/89 , G01J3/50 , G01S7/4816 , G01S17/08 , G01S17/36 , H01L27/0805
摘要： TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X-dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably a potential barrier is implanted between adjacent gates and a bias gate is formed intermediate a gate and associated source region. Resultant detector structures can be operated at the more extreme gate voltages that are desirable for high performance.
摘要翻译： TOF和颜色感测检测器结构具有x轴间隔开的y轴延伸的具有相邻源收集区域的指状栅极结构。 X维结构小于y维结构并且控制性能，其特征在于高x轴电场和快速电荷运动，与较低的y轴电场和较慢的电荷运动形成对比。优选地，在相邻栅极之间注入势垒，并且在栅极和相关源极区之间形成偏压栅极。所产生的检测器结构可以在高性能所需的更极端的栅极电压下工作。

6. 发明申请

US20080007709A1 Method and system for fast calibration of three-dimensional (3D) sensors 有权
公开(公告)号：US20080007709A1
公开(公告)日：2008-01-10
申请号：US11825582
申请日：2007-07-06
申请人： Cyrus Bamji , Hakan Yalcin
发明人： Cyrus Bamji , Hakan Yalcin
IPC分类号： G01C3/08 , G01S7/497
CPC分类号： G01C3/08 , G01C25/00 , G01S7/497 , G01S17/36 , G01S17/89
摘要： Rapid calibration of a TOF system uses a stationary target object and electrically introduces phase shift into the TOF system to emulate target object relocation. Relatively few parameters suffice to model a parameterized mathematical representation of the transfer function between measured phase and Z distance. The phase-vs-distance model is directly evaluated during actual run-time operation of the TOF system. Preferably modeling includes two components: electrical modeling of phase-vs-distance characteristics that depend upon electrical rather than geometric characteristics of the sensing system, and elliptical modeling that phase-vs-distance characteristics that depending upon geometric rather than electrical characteristics of the sensing system.

7. 发明授权

US06919549B2 Method and system to differentially enhance sensor dynamic range 失效
标题翻译：传感器动态范围差异化的方法和系统
公开(公告)号：US06919549B2
公开(公告)日：2005-07-19
申请号：US10823415
申请日：2004-04-12
申请人： Cyrus Bamji , Hakan Yalcin , Xinqiao Liu , Ender Tunc Eroglu
发明人： Cyrus Bamji , Hakan Yalcin , Xinqiao Liu , Ender Tunc Eroglu
IPC分类号： G01C3/08 , G01S7/481 , G01S7/486 , G01S7/491 , G01S17/10 , G01S17/48 , H01J40/14 , H01L27/00 , H04N5/3745
CPC分类号： G01S17/08 , G01C3/08 , G01S7/4813 , G01S7/4863 , G01S7/4868 , G01S7/487 , G01S17/10 , G01S17/89 , H04N5/3745
摘要： Effective differential dynamic range in a differential pixel detector is increased by avoiding saturation effects due to common mode contribution in optical energy to be detected. Photocurrent generated by each photodetector pair is directly integrated by an associated capacitor over an integration time T. Within time T, before either integrated capacitor voltage reaches Vsat for the photodetector, at least one of the capacitors is reset to a voltage such that the desired differential detector signal is still determinable. Reset may be generated externally or internally to the differential pixel detector.
摘要翻译：差分像素检测器中的有效差分动态范围通过避免由于要检测的光能中的共模贡献而导致的饱和效应而增加。由每个光电检测器对产生的光电流在积分时间T上由相关的电容器直接积分。在时间T内，在集成电容器电压达到光电检测器的V S sat之前，至少一个电容器被复位达到使得所需的差分检测器信号仍然可确定的电压。复位可以在差分像素检测器的外部或内部产生。

8. 发明申请

US20050051707A1 METHOD AND SYSTEM TO DIFFERENTIALLY ENHANCE SENSOR DYNAMIC RANGE 失效
标题翻译：方法和系统差分增强传感器动态范围
公开(公告)号：US20050051707A1
公开(公告)日：2005-03-10
申请号：US10823415
申请日：2004-04-12
申请人： Cyrus Bamji , Hakan Yalcin , Xinqiao Liu , Ender Eroglu
发明人： Cyrus Bamji , Hakan Yalcin , Xinqiao Liu , Ender Eroglu
IPC分类号： G01C3/08 , G01S7/481 , G01S7/486 , G01S7/491 , G01S17/10 , G01S17/48 , H01J40/14 , H01L27/00 , H04N5/3745
CPC分类号： G01S17/08 , G01C3/08 , G01S7/4813 , G01S7/4863 , G01S7/4868 , G01S7/487 , G01S17/10 , G01S17/89 , H04N5/3745
摘要： Effective differential dynamic range in a differential pixel detector is increased by avoiding saturation effects due to common mode contribution in optical energy to be detected. Photocurrent generated by each photodetector pair is directly integrated by an associated capacitor over an integration time T. Within time T, before either integrated capacitor voltage reaches Vsat for the photodetector, at least one of the capacitors is reset to a voltage such that the desired differential detector signal is still determinable. Reset may be generated externally or internally to the differential pixel detector.
摘要翻译：差分像素检测器中的有效差分动态范围通过避免由于要检测的光能中的共模贡献而导致的饱和效应而增加。由每个光电检测器对产生的光电流在积分时间T上由相关的电容器直接积分。在时间T内，在集成电容器电压达到光电检测器的Vsat之前，至少一个电容器被复位到电压，使得期望的差分检测器信号仍然可以确定。复位可以在差分像素检测器的外部或内部产生。

9. 发明授权

US07719662B2 Method and system for fast calibration of three-dimensional (3D) sensors 有权
标题翻译：三维（3D）传感器快速校准的方法和系统
公开(公告)号：US07719662B2
公开(公告)日：2010-05-18
申请号：US12319086
申请日：2008-12-30
申请人： Cyrus Bamji , Hakan Yalcin
发明人： Cyrus Bamji , Hakan Yalcin
IPC分类号： G01C3/08
CPC分类号： G01C3/08 , G01C25/00 , G01S7/497 , G01S17/36 , G01S17/89
摘要： Rapid calibration of a TOF system uses a stationary target object and electrically introduces phase shift into the TOF system to emulate target object relocation. Relatively few parameters suffice to model a parameterized mathematical representation of the transfer function between measured phase and Z distance. The phase-vs-distance model is directly evaluated during actual run-time operation of the TOF system. Preferably modeling includes two components: electrical modeling of phase-vs-distance characteristics that depend upon electrical rather than geometric characteristics of the sensing system, and elliptical modeling that phase-vs-distance characteristics that depending upon geometric rather than electrical characteristics of the sensing system.
摘要翻译： TOF系统的快速校准使用固定的目标物体，并将相移电相引入到TOF系统中以模拟目标物体重定位。相对较少的参数足以对测量相位和Z距离之间的传递函数进行参数化数学表示。在TOF系统的实际运行时间期间直接评估相位对距离模型。建模模型最好包括两个部分：取决于传感系统的电而不是几何特性的相位 - 距离特性的电气建模，以及取决于传感系统的几何而不是电特性的相位 - 距离特性的椭圆建模。

10. 发明授权

US07647220B2 Transistor-level timing analysis using embedded simulation 失效
标题翻译：使用嵌入式仿真的晶体管级定时分析
公开(公告)号：US07647220B2
公开(公告)日：2010-01-12
申请号：US10042512
申请日：2001-10-18
申请人： Pawan Kulshreshtha , Robert J. Palermo , Mohammad Mortazavi , Cyrus Bamji , Hakan Yalcin
发明人： Pawan Kulshreshtha , Robert J. Palermo , Mohammad Mortazavi , Cyrus Bamji , Hakan Yalcin
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.
摘要翻译：公开了一种用于晶体管级静态时序分析的高精度方法。精确的静态定时验证要求精确计算各个门和互连延迟。在亚微米级，使用延迟模型计算门和互连延迟可能导致精度降低。相反，所提出的方法通过使用嵌入式电路模拟器的数值积分来计算延迟。考虑到短路电流，并仔细选择导致每个门极差延迟严格上限的一组条件。自动识别电路中相似的重复晶体管配置，并且一种新颖的基于插值的缓存方案可以从相似门的延迟中快速计算门延迟。与商用高速晶体管级电路仿真器紧密的目标代码级集成可以有效地调用仿真。

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