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1. 发明授权

US07414607B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07414607B2
公开(公告)日：2008-08-19
申请号：US10733395
申请日：2003-12-12
申请人： Hajime Washio , Kazuhiro Maeda , Mamoru Onda
发明人： Hajime Washio , Kazuhiro Maeda , Mamoru Onda
IPC分类号： G09G3/36 , G09G5/00 , G06F3/038
CPC分类号： G09G3/3688 , G09G3/3607 , G09G3/3677 , G09G2300/043 , G09G2310/0248 , G09G2320/0223 , G09G2330/021
摘要： In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCK1 and SCK2 are supplied to the first data signal line driving circuit SD1, while the first clock signal SCK1 is also supplied to the second data signal line driving circuit SD2 in parallel. The wirings 1 and 2 for the respective signals are adjusted to have equal wiring load with a dummy wiring 2 provided in the wiring 2, for solving uneven wiring load caused by difference of leading manner, the dummy wiring 2 constituting an additional capacitor section 7, together with a liquid crystal layer and a counter electrode.
摘要翻译：在将这些信号相互关联的多个信号提供给驱动电路的结构中，至少一个信号也被提供给另一个电路的结构中，本发明防止了多个信号之间的相位关系的变化由于接线负载不同，无需直接处理具有较高功耗的信号。第一和第二时钟信号SCK 1和SCK 2被提供给第一数据信号线驱动电路SD 1，而第一时钟信号SCK 1也被并行地提供给第二数据信号线驱动电路SD 2。对于各信号的布线1和2被调整为具有与配线2中设置的虚拟布线2相同的布线负载，用于解决由引导方式的差引起的不均匀布线负载，构成附加电容器部分7的虚拟布线2，与液晶层和对电极一起。

2. 发明授权

US07333096B2 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US07333096B2
公开(公告)日：2008-02-19
申请号：US10316193
申请日：2002-12-11
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制向像素PIX写入的控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

3. 发明申请

US20070146354A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 审中-公开
公开(公告)号：US20070146354A1
公开(公告)日：2007-06-28
申请号：US11634738
申请日：2006-12-05
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

4. 发明授权

US07212184B2 Shift register and image display device 有权
标题翻译：移位寄存器和图像显示设备
公开(公告)号：US07212184B2
公开(公告)日：2007-05-01
申请号：US10800352
申请日：2004-03-12
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.
摘要翻译：在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。此外，使用两种时钟信号，每个时钟信号的占空比不大于50％，并且在其低电平时段中没有重叠部分，以便防止移位寄存器的输出与每个其他。因此，可以提供优选用于图像显示装置的驱动电路的移位寄存器，可以使驱动电路小型化，并且可以期望地改变输出信号的脉冲宽度，并且还提供图像显示装置使用这种移位寄存器。

5. 发明授权

US07190338B2 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US07190338B2
公开(公告)日：2007-03-13
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

6. 发明授权

US07173598B2 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
公开(公告)号：US07173598B2
公开(公告)日：2007-02-06
申请号：US11063718
申请日：2005-02-22
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

7. 发明申请

US20060181502A1 Signal line driving circuit and image display device 审中-公开
公开(公告)号：US20060181502A1
公开(公告)日：2006-08-17
申请号：US11402352
申请日：2006-04-11
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

8. 发明授权

US07034795B2 Matrix image display device 失效
公开(公告)号：US07034795B2
公开(公告)日：2006-04-25
申请号：US10208757
申请日：2002-08-01
申请人： Kazuhiro Maeda , Hajime Washio , Yasushi Kubota
发明人： Kazuhiro Maeda , Hajime Washio , Yasushi Kubota
IPC分类号： G06G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G2310/021 , G09G2310/0251 , G09G2320/0209 , G09G2340/0414
摘要： The scanning signal line driving circuit sequentially carries out active driving with respect to each set of a certain number of scanning signal lines which are adjacent to each other in a vertical direction, and when carrying out an actual writing with respect to a first set of a certain number of pixel lines adjacent to each other in the vertical direction, carries out pre-charging with respect to a second set of the certain number of pixel lines to which the actual writing is carried out next with a potential of a same polarity as that of the first set of the certain number of pixel lines. In this manner, it is possible to provide a matrix image display device with no irregularities in display quality and is capable of matching the apparent vertical resolution of the device to that of the image source, when using an image signal of vertical resolution lower than the maximum physical vertical resolution of the device.

9. 发明授权

US06836269B2 Precharge circuit and image display device using the same 有权
标题翻译：预充电电路和使用其的图像显示装置
公开(公告)号：US06836269B2
公开(公告)日：2004-12-28
申请号：US09795658
申请日：2001-02-28
申请人： Kazuhiro Maeda , Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Kazuhiro Maeda , Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G500
CPC分类号： G09G3/3688 , G09G2310/0248 , G09G2310/0289 , G09G2330/021
摘要： A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.
摘要翻译：一种预充电控制电路，包括：（1）安装在预充电电路中的锁存电路和（2）通过锁存电路的输出控制的电流驱动型电平移位电路。预充电控制电路将锁存电路改变为有效状态，使得电流驱动类型的电平移动电路仅在预充电期间以及在紧接之前和之后周期期间操作，并且在这些周期之外，将锁存电路改变为非活动状态和电流驱动类型的电平移位器电路，以在电平移位器电路中节省功耗。这使得能够提供低功耗预充电电路以及具有高质量显示能力的低功耗图像显示装置。

10. 发明授权

US06724363B1 Two-way shift register and image display device using the same 有权
公开(公告)号：US06724363B1
公开(公告)日：2004-04-20
申请号：US09568889
申请日：2000-05-11
申请人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
发明人： Masakazu Satoh , Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G336
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G09G2310/0283 , G09G2310/0289 , G09G2330/021 , G11C19/28
摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.

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