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1. 发明申请

US20050243588A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US20050243588A1
公开(公告)日：2005-11-03
申请号：US11091012
申请日：2005-03-25
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00 , H01L21/77 , H01L21/84 , G11C5/06
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

2. 发明申请

US20070146354A1 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 审中-公开
公开(公告)号：US20070146354A1
公开(公告)日：2007-06-28
申请号：US11634738
申请日：2006-12-05
申请人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael Brownlow , Graham Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

3. 发明申请

US20060181502A1 Signal line driving circuit and image display device 审中-公开
公开(公告)号：US20060181502A1
公开(公告)日：2006-08-17
申请号：US11402352
申请日：2006-04-11
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Cairns , Michael Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

4. 发明授权

US07339570B2 Data signal line drive circuit, drive circuit, image display device incorporating the same, and electronic apparatus using the same 有权
标题翻译：数据信号线驱动电路，驱动电路，并入其的图像显示装置，以及使用该数据信号线的电子装置
公开(公告)号：US07339570B2
公开(公告)日：2008-03-04
申请号：US09851885
申请日：2001-05-09
申请人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
发明人： Yasushi Kubota , Hajime Washio , Michael James Brownlow , Graham Andrew Cairns , Yasuyoshi Kaise , Kazuhiro Maeda
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G5/005 , G09G5/006 , G09G2300/0456 , G09G2310/0205 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0294 , G09G2320/0626 , G09G2330/021 , G09G2340/0428 , G09G2340/10 , G09G2340/12 , G09G2360/144 , H01L27/124 , H04N2007/145
摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
摘要翻译：图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

5. 发明授权

US06909417B2 Shift register and image display apparatus using the same 有权
标题翻译：移位寄存器和使用其的图像显示装置
公开(公告)号：US06909417B2
公开(公告)日：2005-06-21
申请号：US09578440
申请日：2000-05-25
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G11C19/00 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G2300/0408 , G09G2310/0289 , G09G2330/021
摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.
摘要翻译：为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗的正常运行中的移位寄存器。

6. 发明授权

US06879313B1 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
标题翻译：移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法
公开(公告)号：US06879313B1
公开(公告)日：2005-04-12
申请号：US09523511
申请日：2000-03-10
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida , Kazuhiro Maeda , Hiroshi Yoneda
IPC分类号： G09G3/36 , G11C19/28 , G11C19/00
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.
摘要翻译：移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路线和多个锁存电路。在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

7. 发明授权

US06853324B2 Digital-to-analog conversion circuit and image display apparatus using the same 有权
标题翻译：数模转换电路和使用其的图像显示装置
公开(公告)号：US06853324B2
公开(公告)日：2005-02-08
申请号：US09952183
申请日：2001-09-13
申请人： Kazuhiro Maeda , Yasushi Kubota , Hajime Washio
发明人： Kazuhiro Maeda , Yasushi Kubota , Hajime Washio
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1368 , G09G3/20 , G09G3/36 , H03M1/74 , H03M1/80 , H03M1/66
CPC分类号： H03M1/804 , G09G3/3688 , G09G2310/027
摘要： A digital-to-analog conversion circuit of charge distribution type includes a plurality of capacitors having respective capacitances that increase in a sequential order, one end of the capacitors being commonly connected electrically. The circuit also includes a plurality of analog switches each for electrically connecting a reference potential corresponding to a digital signal inputted from outside to the other end of the corresponding capacitor. These analog switches have respective driving capacities that increase in a sequential order.
摘要翻译：电荷分配型的数模转换电路包括多个电容器，其具有各自依次增加的电容，电容器的一端电连接。电路还包括多个模拟开关，每个模拟开关用于将与从外部输入的数字信号相对应的参考电位电连接到对应的电容器的另一端。这些模拟开关具有按照顺序增加的各自的驱动能力。

8. 发明申请

US20090009374A1 DIGITAL TO ANALOGUE CONVERTER 失效
标题翻译：数字到模拟转换器
公开(公告)号：US20090009374A1
公开(公告)日：2009-01-08
申请号：US11793522
申请日：2006-01-11
申请人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
发明人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
IPC分类号： H03M1/66
CPC分类号： H03M1/802
摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.
摘要翻译：一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1））开关电容器; 和切换装置。在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入所述至少一个电容器。在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

9. 发明申请

US20080036753A1 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US20080036753A1
公开(公告)日：2008-02-14
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW，不仅在第一帧中显示，而且在预定数量的帧中显示一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

10. 发明授权

US07042433B1 Signal line driving circuit and image display device 有权
标题翻译：信号线驱动电路和图像显示装置
公开(公告)号：US07042433B1
公开(公告)日：2006-05-09
申请号：US09567364
申请日：2000-05-09
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Andrew Cairns , Michael James Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.
摘要翻译：信号线驱动电路包括具有多个移位电路的移位寄存器，每个移位电路将开始脉冲连续地移位到下一级，与时钟信号的定时同步。在该信号线驱动电路中，基于两个相邻移位电路的输出脉冲，从与门输出移位脉冲。同时，用于指定移位脉冲的脉冲宽度的宽度指定脉冲通过由移位脉冲控制其ON / OFF操作的晶体管输入。逻辑运算电路对移位脉冲和宽度指定脉冲进行AND运算，并将运算结果输出到信号线。当移位脉冲不起作用时，晶体管变为截止，使得将信号线发送宽度指定脉冲与信号线驱动电路断开，从而降低布线的容性负载。结果，实现了信号线驱动电路中布线的寄生电容的减小，元件数目的减少，输入信号的幅度的减小等。

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