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1. 发明申请

US20060076624A1 Semiconductor substrate, method of manufacturing the same, semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体衬底及其制造方法，半导体器件及其制造方法
公开(公告)号：US20060076624A1
公开(公告)日：2006-04-13
申请号：US11282784
申请日：2005-11-18
申请人： Hajime Nagano , Kiyotaka Miyano , Ichiro Mizushima
发明人： Hajime Nagano , Kiyotaka Miyano , Ichiro Mizushima
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/76251 , H01L21/84
摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.
摘要翻译：公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层，不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面层位于绝缘体上。

2. 发明授权

US07122864B2 Semiconductor substrate having a partial SOI structure, method of manufacturing the same, a semiconductor device having a partial SOI structure, and method of manufacturing the same 有权
标题翻译：具有部分SOI结构的半导体衬底及其制造方法，具有部分SOI结构的半导体器件及其制造方法
公开(公告)号：US07122864B2
公开(公告)日：2006-10-17
申请号：US10439896
申请日：2003-05-16
申请人： Hajime Nagano , Kiyotaka Miyano , Ichiro Mizushima
发明人： Hajime Nagano , Kiyotaka Miyano , Ichiro Mizushima
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/76251 , H01L21/84
摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.
摘要翻译：公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层，不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面层位于绝缘体上。

3. 发明授权

US07525154B2 Semiconductor substrate, manufacturing method therefor, and semiconductor device 失效
标题翻译：半导体衬底及其制造方法和半导体器件
公开(公告)号：US07525154B2
公开(公告)日：2009-04-28
申请号：US10852511
申请日：2004-05-25
申请人： Hajime Nagano , Ichiro Mizushima , Kiyotaka Miyano
发明人： Hajime Nagano , Ichiro Mizushima , Kiyotaka Miyano
IPC分类号： H01L29/72
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/78687
摘要： A semiconductor substrate and a manufacturing method therefore, and a semiconductor device using the semiconductor substrate comprise a strained Si region and unstrained Si region formed at substantially the same level. In an aspect of the invention, a semiconductor substrate is provided by comprising a support substrate, a first semiconductor region including a first silicon layer formed above the support substrate, a second semiconductor region including a strained second silicon layer formed above the support substrate, a surface of the second silicon layer being formed at substantially the same level as a surface of the first silicon layer, and an insulating film at an interface between the first semiconductor region and the second semiconductor region.
摘要翻译：因此，半导体衬底及其制造方法以及使用该半导体衬底的半导体器件包括形成在大致相同电平的应变Si区域和未应变Si区域。在本发明的一个方面中，提供一种半导体衬底，其包括支撑衬底，包括形成在支撑衬底上方的第一硅层的第一半导体区域，包括形成在支撑衬底上方的应变第二硅层的第二半导体区域，所述第二硅层的表面形成在与所述第一硅层的表面基本相同的水平面上，以及在所述第一半导体区域和所述第二半导体区域之间的界面处形成绝缘膜。

4. 发明授权

US07294562B2 Semiconductor substrate, method of manufacturing the same, semiconductor device, and method of manufacturing the same 有权
标题翻译：半导体衬底及其制造方法，半导体器件及其制造方法
公开(公告)号：US07294562B2
公开(公告)日：2007-11-13
申请号：US11282784
申请日：2005-11-18
申请人： Hajime Nagano , Kiyotaka Miyano , Ichiro Mizushima
发明人： Hajime Nagano , Kiyotaka Miyano , Ichiro Mizushima
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L21/76251 , H01L21/84
摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.
摘要翻译：公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层，不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面层位于绝缘体上。

5. 发明申请

US20050205929A1 Semiconductor substrate, manufacturing method therefor, and semiconductor device 失效
标题翻译：半导体衬底及其制造方法和半导体器件
公开(公告)号：US20050205929A1
公开(公告)日：2005-09-22
申请号：US10852511
申请日：2004-05-25
申请人： Hajime Nagano , Ichiro Mizushima , Kiyotaka Miyano
发明人： Hajime Nagano , Ichiro Mizushima , Kiyotaka Miyano
IPC分类号： H01L27/08 , H01L21/02 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/04 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/739 , H01L29/78 , H01L29/786
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/78687
摘要： A semiconductor substrate and a manufacturing method therefore, and a semiconductor device using the semiconductor substrate comprise a strained Si region and unstrained Si region formed at substantially the same level. In an aspect of the invention, a semiconductor substrate is provided by comprising a support substrate, a first semiconductor region including a first silicon layer formed above the support substrate, a second semiconductor region including a strained second silicon layer formed above the support substrate, a surface of the second silicon layer being formed at substantially the same level as a surface of the first silicon layer, and an insulating film at an interface between the first semiconductor region and the second semiconductor region.
摘要翻译：因此，半导体衬底及其制造方法以及使用该半导体衬底的半导体器件包括形成在大致相同电平的应变Si区域和未应变Si区域。在本发明的一个方面中，提供一种半导体衬底，其包括支撑衬底，包括形成在支撑衬底上方的第一硅层的第一半导体区域，包括形成在支撑衬底上方的应变第二硅层的第二半导体区域，所述第二硅层的表面形成在与所述第一硅层的表面基本相同的水平面上，以及在所述第一半导体区域和所述第二半导体区域之间的界面处形成绝缘膜。

6. 发明申请

US20060194405A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060194405A1
公开(公告)日：2006-08-31
申请号：US11266262
申请日：2005-11-04
申请人： Hajime Nagano , Kiyotaka Miyano , Osamu Arisumi
发明人： Hajime Nagano , Kiyotaka Miyano , Osamu Arisumi
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A semiconductor device has an element isolating region formed of an insulating film having etching rates different from each other in a side close to an inside wall and a center side of a trench formed on a semiconductor substrate, and a selective epitaxial layer formed in both sides of the element isolating region, wherein the element isolating region has a tip portion in a tapered shape or a stepwise shape of which a width becomes narrower at a side closer to the tip portion.
摘要翻译：半导体器件具有由绝缘膜形成的元件隔离区，该绝缘膜具有在靠近半导体衬底上形成的沟槽的内壁和中心侧的蚀刻速率彼此不同的蚀刻速率，以及形成在两侧的选择性外延层所述元件隔离区域具有锥形形状的尖端部分或在靠近所述尖端部分的一侧宽度变窄的阶梯形状。

7. 发明授权

US07718483B2 Method of manufacturing non-volatile semiconductor memory 失效
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US07718483B2
公开(公告)日：2010-05-18
申请号：US11399655
申请日：2006-04-07
申请人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
发明人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译：在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

8. 发明授权

US07265017B2 Method for manufacturing partial SOI substrates 失效
标题翻译：制造部分SOI衬底的方法
公开(公告)号：US07265017B2
公开(公告)日：2007-09-04
申请号：US11168914
申请日：2005-06-29
申请人： Hajime Nagano , Ichiro Mizushima
发明人： Hajime Nagano , Ichiro Mizushima
IPC分类号： H01L21/331
CPC分类号： H01L27/1203 , H01L21/84
摘要： There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.
摘要翻译：封闭半导体器件，其包括半导体衬底，该半导体衬底包括掩埋有第一绝缘膜的SOI区域和非SOI区域，该半导体衬底设置有形成在SOI区域与非SOI区域之间的边界区域并且具有埋置在其中的第二绝缘膜，所述第二绝缘膜从所述SOI区域侧向非SOI区域侧向上倾斜，所述第二绝缘膜的厚度小于所述第一绝缘膜的厚度， SOI区域侧，分离地形成在半导体衬底的非SOI区域中并限定元件区域的一对元件隔离绝缘区域，形成在元件区域中的一对杂质扩散区域以及栅极电极通过半导体衬底的元件区域中的栅极绝缘膜形成。

9. 发明申请

US20060258076A1 Method of manufacturing non-volatile semiconductor memory 失效
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US20060258076A1
公开(公告)日：2006-11-16
申请号：US11399655
申请日：2006-04-07
申请人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
发明人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译：在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

10. 发明授权

US06906384B2 Semiconductor device having one of patterned SOI and SON structure 失效
标题翻译：具有图案化SOI和SON结构之一的半导体器件
公开(公告)号：US06906384B2
公开(公告)日：2005-06-14
申请号：US10096655
申请日：2002-03-14
申请人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
发明人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
IPC分类号： H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/10861 , H01L21/76243 , H01L21/823481 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1203 , H01L29/78639
摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.
摘要翻译：半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。第一半导体层设置在半导体衬底上并与之电连接。第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

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