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1. 发明授权

US5321387A Associative storage for data packets including asynchronous, self-running shift register transmission paths 失效
标题翻译：数据包的关联存储，包括异步，自运行移位寄存器传输路径
公开(公告)号：US5321387A
公开(公告)日：1994-06-14
申请号：US99803
申请日：1993-07-29
申请人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori
发明人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori
IPC分类号： G06F15/173 , G11C15/00 , G11C19/00 , G06F7/04 , G06F7/06
CPC分类号： G06F15/17337 , G11C15/00 , G11C19/00
摘要： An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.
摘要翻译：关联存储器包括两个数据传输路径，每个数据传输路径包括以循环方式形成的自运行移位寄存器。在相应的数据传输路径中，每个具有识别数据的数据包被发送到移位寄存器的各个级。从移位寄存器上发送的数据包中提取识别数据，并在比较电路中进行比较。如果并且当在各个传输路径上分别发送的两个数据分组的识别数据一致时，那两个数据分组被确定为要配对的数据分组。从数据传输路径读取数据包对。

2. 发明授权

US4943916A Information processing apparatus for a data flow computer 失效
标题翻译：一种用于数据流计算机的信息处理装置
公开(公告)号：US4943916A
公开(公告)日：1990-07-24
申请号：US361701
申请日：1989-06-01
申请人： Hajime Asano , Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto
发明人： Hajime Asano , Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto
IPC分类号： G06F15/82 , G06F9/38 , G06F9/44
CPC分类号： G06F9/4436 , G06F9/38
摘要： By providing a tag data renewing unit in a data flow-computer, the "delay" function, which is necessary for a digital filter, etc., can be realized, and it is unnecessary to keep the order relation for tokens with respect to first-in/first-out, which must be kept at respective points in a conventional data flow computer, and thereby the architecture of a compiler can be simplified and at the same time the execution time can be shortened.
摘要翻译：通过在数据流计算机中提供标签数据更新单元，可以实现数字滤波器等所必需的“延迟”功能，并且不需要保持令牌相对于第一 -in / first-out，其必须保存在常规数据流计算机的各个点处，从而可以简化编译器的架构，同时可以缩短执行时间。

3. 发明授权

US4972445A Data transmission apparatus 失效
标题翻译：数据传输装置
公开(公告)号：US4972445A
公开(公告)日：1990-11-20
申请号：US432355
申请日：1989-11-06
申请人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
发明人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
IPC分类号： G06F13/42
CPC分类号： G06F13/4217
摘要： A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.
摘要翻译：一种用于在系统之间传输数据的数据传输装置包括：输入数据传输路径，输出数据传输路径和分支数据传输路径，每个移位寄存器由移位寄存器构成，每个数据传输路径都有多个数据存储电路和多个数据传输路径的转移控制电路各自对应于每个o级。数据存储电路根据来自相邻级的传送控制电路的控制信号来控制自身级数据存储电路。提供了一种用于初始化设备的初始化电路，使得数据传输路径上的数据不会保留在设备的操作开始。

4. 发明授权

US4881196A Data transmission line branching system 失效
标题翻译：数据传输线分支系统
公开(公告)号：US4881196A
公开(公告)日：1989-11-14
申请号：US830750
申请日：1986-02-19
申请人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Shinji Komori , Kenji Shima , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
发明人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Shinji Komori , Kenji Shima , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
IPC分类号： H04J3/08 , H04L12/00
CPC分类号： H04L12/00 , H04J3/08
摘要： A data transmission system comprises an input data transmission line (1), an output data transmission line (4), a branching data transmission line (5) and a jointing data transmission line (7) formed respectively by asynchronous free-running shift registers using a plurality of data latches (101 to 106, 401 & 402, 501 & 502, 701 & 702) and, C elements (111 to 116, 411 & 412, 511 & 512, 711 & 712) respectively. A branching control circuit 3 supplies data to be branched to the branching data transmission line (5) in response to the decision by a branching decision circuit (2) as to the fact that the data to be branched is transmitted on the input data transmission line (1). A jointing control circuit (6) supplies data to be joined to the output data transmission line (4) in response to the decision by an empty buffer verifier (8) as to the nonexistence of data in the input data transmission line (1) and the output data transmission line (4) when the data to be jointed is transmitted on the jointing data transmission line (7). Thus, the data transmission system has branching and jointing functions and if it is used as a constituent of a network, data can be transmitted among asynchronous systems.
摘要翻译：数据传输系统包括分别由异步自由运行移位寄存器形成的输入数据传输线（1），输出数据传输线（4），分支数据传输线（5）和连接数据传输线（7）多个数据锁存器（101至106,401和402,501,502,701和702）和C个元件（111至116,411和412,511和512,711和712）。分支控制电路3响应于分支决定电路（2）的决定，将要分支的数据提供给分支数据传输线（5），关于在输入数据传输线上发送待分支数据的事实（1）。接合控制电路（6）响应于空缓冲验证器（8）对输入数据传输线（1）中的数据的不存在以及对输入数据传输线（4）中的数据的不存在的决定，提供要连接到输出数据传输线（4）的数据，以及当连接数据传输线（7）发送要连接的数据时的输出数据传输线（4）。因此，数据传输系统具有分支和联合功能，并且如果它被用作网络的组成部分，则可以在异步系统之间传输数据。

5. 发明授权

US4841436A Tag Data processing apparatus for a data flow computer 失效
标题翻译：标签数据流计算机的数据处理装置
公开(公告)号：US4841436A
公开(公告)日：1989-06-20
申请号：US868701
申请日：1986-05-30
申请人： Hajime Asano , Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto
发明人： Hajime Asano , Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto
IPC分类号： G06F15/82 , G06F9/44
CPC分类号： G06F9/4436
摘要： A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.
摘要翻译：描述了使用标记令牌方案的数据流计算机中使用的标签数据处理装置。通过使用流水线寄存器，队列存储器和简单控制电路来执行标签添加处理和标签恢复处理，从而获得高速操作和优异的吞吐量，而不需要标签存储表，复杂的操作测试电路或序列控制电路。

6. 发明授权

US4785204A Coincidence element and a data transmission path 失效
标题翻译：一致元素和数据传输路径
公开(公告)号：US4785204A
公开(公告)日：1988-11-15
申请号：US875551
申请日：1986-06-18
申请人： Hiroaki Terada , Katsuhiko Asada , Niroaki Nishikawa , Shinji Komori , Kenji Shima , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
发明人： Hiroaki Terada , Katsuhiko Asada , Niroaki Nishikawa , Shinji Komori , Kenji Shima , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
IPC分类号： H03K19/21 , H03K3/353 , H03K3/286 , H03K21/17 , H03K23/44
CPC分类号： H03K19/215
摘要： A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.
摘要翻译：当所述多个输入信号彼此一致时，响应于多个输入信号用于输出输入信号的电平的符合元件包括：第一导电类型和第二导电类型的MOS晶体管的串联连接数量等于输入信号的数量，响应于连接在第一电源和第二电源之间的所述多个输入; 以及响应于在最下级第一导电类型MOS晶体管和最上层第二导电类型MOS晶体管的连接处的中间输出的CMOS反相器，用于输出一致信号。

7. 发明授权

US4918644A System containing loop shaped transmission paths for transmitting data packets using a plurality of latches connected in cascade fashion 失效
标题翻译：包含环形传输路径的系统，用于使用以级联方式连接的多个锁存器传输数据包
公开(公告)号：US4918644A
公开(公告)日：1990-04-17
申请号：US868291
申请日：1986-05-28
申请人： Hiroaki Terada , Katushiko Asada , Hiroaki Nishikawa , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori
发明人： Hiroaki Terada , Katushiko Asada , Hiroaki Nishikawa , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura , Kenji Shima , Shinji Komori
IPC分类号： G06F7/78
CPC分类号： G06F7/78
摘要： A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.
摘要翻译：数据处理装置包括以循环方式同样形成的两个数据传输路径。这些数据传输路径分别包括以级联方式连接的多个锁存寄存器，并且被构成为所谓的自运行型移位寄存器，其中构成数据包的每个数据字按顺序移位，前提是前级寄存器是空的。数据分组在两个环形数据传输路径上沿相反的方向发送，在被定义为数据分组对检测部分的部分中检测到正在发送的每个数据分组中包括的标识数据。检测到的识别数据在比较电路中进行比较，并且以数据分组从一个数据传输路径连接到另一个数据传输路径的方式从两个数据分组产生一个新的数据分组。

8. 发明授权

US4907187A Processing system using cascaded latches in a transmission path for both feedback and forward transfer of data 失效
标题翻译：在传输路径中使用级联锁存器的处理系统用于数据的反馈和正向传送
公开(公告)号：US4907187A
公开(公告)日：1990-03-06
申请号：US863979
申请日：1986-05-16
申请人： Hiroaki Terada , Katsuhiko Asada , Niroaki Nishikawa , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura , Kenji Shima
发明人： Hiroaki Terada , Katsuhiko Asada , Niroaki Nishikawa , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura , Kenji Shima
IPC分类号： G06F7/48 , G06F9/44
CPC分类号： G06F9/4436 , G06F7/48
摘要： A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.
摘要翻译：数据处理装置包括自运行型移位寄存器，该移位寄存器包括以级联方式布置的多个锁存寄存器。锁存寄存器以字为单位锁存数据包。在每个锁存寄存器中，与之相关联地设置符合元件，并且如果前级锁存器寄存器为空，这些符合元件允许来自后级锁存器寄存器的数据传送。数据处理元件安装在两个锁存寄存器之间，并且数据处理元件响应于由前一个字中包含的操作代码所示的处理类型，处理来自两个锁存器寄存器中的一个或两者的操作数数据。当前级锁存寄存器在重合元件的控制下处于空闲状态时，处理结果被传送到前级锁存寄存器。

9. 发明授权

US5165036A Parallel processing development system with debugging device includes facilities for schematically displaying execution state of data driven type processor 失效
标题翻译：具有调试装置的并行处理开发系统包括用于示意性地显示数据驱动型处理器的执行状态的设备
公开(公告)号：US5165036A
公开(公告)日：1992-11-17
申请号：US471204
申请日：1990-01-29
申请人： Souichi Miyata , Satoshi Matsumoto , Shin'ichi Yoshida , Toshiya Okamoto , Takeshi Fukuhara , Shinji Komori , Tetsuo Yamasaki , Kenji Shima
发明人： Souichi Miyata , Satoshi Matsumoto , Shin'ichi Yoshida , Toshiya Okamoto , Takeshi Fukuhara , Shinji Komori , Tetsuo Yamasaki , Kenji Shima
IPC分类号： G06F9/44 , G06F11/36
CPC分类号： G06F11/3664 , G06F11/3636 , G06F9/4436
摘要： A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.
摘要翻译：并行处理器显影系统包括控制计算机，接口部分，处理元件，示踪部分和显示部分。处理元件包括数据驱动型处理器。接口部分存储从控制计算机提供的数据包，并以预定的时间间隔将数据包应用于处理元件。跟踪器部分将处理元件的预定端口提供的数据包与时间信息一起存储。显示部分显示示踪部分的存储内容。

10. 发明授权

US5133054A Data transmission apparatus for autonomously and selectively transmitting data to a plurality of transfer path 失效
标题翻译：数据发送装置，用于自动和选择性地将数据发送到多个传送路径
公开(公告)号：US5133054A
公开(公告)日：1992-07-21
申请号：US259850
申请日：1988-10-19
申请人： Satoshi Matsumoto , Souichi Miyata
发明人： Satoshi Matsumoto , Souichi Miyata
IPC分类号： G06F13/40
CPC分类号： G06F13/4022
摘要： A data transmission apparatus including an input-side data transmission path having a first-stage data transmission path, a second-stage data transmission path and a plurality of output-side data transfer paths is provided. When data, which include an identifier for designating the output-side data, transfer path are carried on the input-side transmission path, a comparison/decision logic unit compares the identifier in the data to be transferred and a data destination bit separately supplied thereto. The compared results are supplied to a branch control which produces a select bit for specifying one of the plurality of the outgoing data transfer paths. The incoming data together with a sending signal are passed through the first and second stage input-side data transmission paths toward the plurality of the output-side data transfer paths. The data are then transferred through one particular output-side data transfer path selected by the application of a select bit supplied thereto.
摘要翻译：提供了包括具有第一级数据传输路径，第二级数据传输路径和多个输出侧数据传输路径的输入侧数据传输路径的数据传输设备。当包括用于指定输出侧数据的标识符的传输路径的数据在输入侧传输路径上传送时，比较/判定逻辑单元将要传送的数据中的标识符与分别提供给它的数据目的地比特。将比较结果提供给分支控制，该分支控制产生用于指定多个输出数据传送路径中的一个的选择位。输入数据与发送信号一起通过第一和第二级输入侧数据传输路径朝向多个输出侧数据传送路径。然后通过应用提供给它的选择位选择的一个特定的输出侧数据传输路径传输数据。

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