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1. 发明申请

US20130134295A1 IMAGING SYSTEMS WITH SELECTABLE COLUMN POWER CONTROL 有权
标题翻译：具有可选列功率控制的成像系统
公开(公告)号：US20130134295A1
公开(公告)日：2013-05-30
申请号：US13485867
申请日：2012-05-31
申请人： Hai Yan , Ashirwad Bahukhandi
发明人： Hai Yan , Ashirwad Bahukhandi
IPC分类号： H01L27/146
CPC分类号： H01L27/146 , H04N5/345 , H04N5/3698
摘要： Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry. The column readout circuitry on each column line may include signal processing circuitry and a latch circuit. The latch circuit on each column line may be used to selectively enable and disable the signal processing circuitry on that column line. Each latch circuit may be coupled to first and second signal lines for globally enabling and disabling the signal processing circuitry on all of the column lines. Each latch circuit may be coupled to column decoder circuitry. The column decoder circuitry may provide a column-select signal to latch circuits on a chosen subset of column lines that enables the signal processing circuitry on those column lines by setting those latch circuits.
摘要翻译：电子设备可以包括具有图像像素阵列的图像传感器，图像像素排列成像素行和像素列。每个像素列可以耦合到具有列读出电路的列线。每列列线上的列读出电路可以包括信号处理电路和锁存电路。每个列线上的锁存电路可以用于选择性地启用和禁用该列线路上的信号处理电路。每个锁存电路可以耦合到第一和第二信号线，以全局启用和禁用所有列线路上的信号处理电路。每个锁存电路可以耦合到列解码器电路。列解码器电路可以通过设置这些锁存电路来在选定的列线子集上的锁存电路上提供列选择信号，从而使这些列线路上的信号处理电路能够实现。

2. 发明授权

US08817153B2 Column parallel readout image sensors with shared column analog-to-digital converter circuitry 有权
标题翻译：具有共享列模数转换器电路的列并行读出图像传感器
公开(公告)号：US08817153B2
公开(公告)日：2014-08-26
申请号：US13550573
申请日：2012-07-16
申请人： Ashirwad Bahukhandi , Hai Yan
发明人： Ashirwad Bahukhandi , Hai Yan
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/37455 , H04N5/3742 , H04N5/378
摘要： Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array.
摘要翻译：电子设备可以包括具有以行和列排列的图像传感器像素的图像传感器。沿着列排列的像素可以耦合到公共列线。两个或更多个列线可以通过耦合到共享的模数转换器电路。共享模数转换器电路可采样和保持列线上呈现的复位电平或图像电平。共享的模数转换器电路可以将电压预放大并转换成数字信号。共享模数转换器可以同时对像素阵列的所选行中的所有列进行像素电压的采样。图像传感器可以读取存储器中转换的信号用于像素阵列中的活动行，同时对像素阵列的下一行进行采样并保持电压。

3. 发明授权

US09053993B2 Imaging systems with selectable column power control 有权
标题翻译：具有可选列功率控制的成像系统
公开(公告)号：US09053993B2
公开(公告)日：2015-06-09
申请号：US13485867
申请日：2012-05-31
申请人： Hai Yan , Ashirwad Bahukhandi
发明人： Hai Yan , Ashirwad Bahukhandi
IPC分类号： H04N5/335 , H01L27/00 , H01L27/146 , H04N5/345 , H04N5/369
CPC分类号： H01L27/146 , H04N5/345 , H04N5/3698
摘要： Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry. The column readout circuitry on each column line may include signal processing circuitry and a latch circuit. The latch circuit on each column line may be used to selectively enable and disable the signal processing circuitry on that column line. Each latch circuit may be coupled to first and second signal lines for globally enabling and disabling the signal processing circuitry on all of the column lines. Each latch circuit may be coupled to column decoder circuitry. The column decoder circuitry may provide a column-select signal to latch circuits on a chosen subset of column lines that enables the signal processing circuitry on those column lines by setting those latch circuits.
摘要翻译：电子设备可以包括具有图像像素阵列的图像传感器，图像像素排列成像素行和像素列。每个像素列可以耦合到具有列读出电路的列线。每列列线上的列读出电路可以包括信号处理电路和锁存电路。每个列线上的锁存电路可以用于选择性地启用和禁用该列线路上的信号处理电路。每个锁存电路可以耦合到第一和第二信号线，以全局启用和禁用所有列线上的信号处理电路。每个锁存电路可以耦合到列解码器电路。列解码器电路可以通过设置这些锁存电路来在选定的列线子集上的锁存电路上提供列选择信号，从而使这些列线路上的信号处理电路能够实现。

4. 发明申请

US20130070135A1 COLUMN PARALLEL READOUT IMAGE SENSORS WITH SHARED COLUMN ANALOG-TO-DIGITAL CONVERTER CIRCUITRY 有权
标题翻译：具有共享列的模拟和数字转换器电路的并行读数图像传感器
公开(公告)号：US20130070135A1
公开(公告)日：2013-03-21
申请号：US13550573
申请日：2012-07-16
申请人： Ashirwad Bahukhandi , Hai Yan
发明人： Ashirwad Bahukhandi , Hai Yan
IPC分类号： H04N5/3745
CPC分类号： H04N5/37455 , H04N5/3742 , H04N5/378
摘要： Electronic devices may include image sensors having image sensor pixels arranged in rows and columns. Pixels arranged along a column may be coupled to a common column line. Two or more column lines may by coupled to a shared analog-to-digital converter circuit. The shared analog to digital converter circuit may sample and hold reset-level or image-level voltages presented on the column line. The shared analog to digital converter circuits may pre-amplify and convert the voltages to digital signals. The shared analog-to-digital converter may simultaneously sample pixel voltages for all columns in a selected row of the pixel array. The image sensor may read the converted signals out of memory for an active row in the pixel array while simultaneously sampling and holding the voltages for the next row of the pixel array.
摘要翻译：电子设备可以包括具有以行和列排列的图像传感器像素的图像传感器。沿着列排列的像素可以耦合到公共列线。两个或更多个列线可以通过耦合到共享的模数转换器电路。共享模数转换器电路可采样和保持列线上呈现的复位电平或图像电平。共享的模数转换器电路可以将电压预放大并转换成数字信号。共享模数转换器可以同时对像素阵列的所选行中的所有列进行像素电压的采样。图像传感器可以读取存储器中转换的信号用于像素阵列中的活动行，同时对像素阵列的下一行进行采样并保持电压。

5. 发明授权

US09450596B2 Ramp and successive approximation register analog to digital conversion methods, systems and apparatus 有权
标题翻译：斜坡和逐次逼近寄存器模数转换方法，系统和装置
公开(公告)号：US09450596B2
公开(公告)日：2016-09-20
申请号：US13228502
申请日：2011-09-09
申请人： Dongsoo Kim , Taehee Cho , Isao Takayanagi , Ashirwad Bahukhandi , Chiajen Lee
发明人： Dongsoo Kim , Taehee Cho , Isao Takayanagi , Ashirwad Bahukhandi , Chiajen Lee
IPC分类号： H03M1/50 , H03M1/12 , H04N5/378 , H03M1/14 , H03M1/46 , H03M1/56
CPC分类号： H03M1/122 , H03M1/14 , H03M1/46 , H03M1/56 , H04N5/378
摘要： Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.
摘要翻译：公开了逐次逼近寄存器（SAR）和斜坡模数转换（ADC）方法，系统和装置。通过对模拟电压信号执行SAR转换，通过产生多位数字值的位来将模拟电压信号转换为多位数字值，其中对应于SAR电压电平的位，并产生多个数位值的其他位通过对模拟电压信号执行一个或多个斜坡转换，斜坡转换将模拟电压信号与基于SAR电压电平的电压电平斜坡进行比较。 SAR和斜坡ADC可以使用一个SAR转换和多个斜坡转换来提供多采样。 SAR可以设置多个斜坡转换的第一个斜坡的电压电平，然后可以将其用于在随后的斜坡之前预设电压电平。

6. 发明申请

US20080048770A1 MASTER BIAS CURRENT GENERATING CIRCUIT WITH DECREASED SENSITIVITY TO SILICON PROCESS VARIATION 有权
标题翻译：主要偏置电流产生电路对硅工艺变化具有降低的灵敏度
公开(公告)号：US20080048770A1
公开(公告)日：2008-02-28
申请号：US11467314
申请日：2006-08-25
申请人： Ali E. Zadeh , Ashirwad Bahukhandi
发明人： Ali E. Zadeh , Ashirwad Bahukhandi
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.
摘要翻译：主偏置电流产生电路包括电流源，第一参考腿和第二参考腿。第一参考支路包括具有耦合到电流源的第一尺寸参数的第一晶体管和具有耦合到第一晶体管的第二尺寸参数的第一二极管。第二参考支路包括具有小于耦合到电流源的第一尺寸参数的第三尺寸参数的第二晶体管，以及具有大于耦合到第二晶体管的第二尺寸参数的第四尺寸参数的第二二极管。

7. 发明授权

US08581761B1 Methods and apparatus for performing code correction for hybrid analog-to-digital converters in imaging devices 有权
标题翻译：用于对成像装置中的混合模数转换器执行代码校正的方法和装置
公开(公告)号：US08581761B1
公开(公告)日：2013-11-12
申请号：US13650434
申请日：2012-10-12
申请人： Ashirwad Bahukhandi , Taehee Cho , Ju-Hyung Kim
发明人： Ashirwad Bahukhandi , Taehee Cho , Ju-Hyung Kim
IPC分类号： H03M1/06
CPC分类号： H03M1/0863 , H03M1/145 , H03M1/466 , H03M1/56
摘要： Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.
摘要翻译：电子设备可以包括具有图像传感器像素的图像传感器。像素可以耦合到模数转换器（ADC）电路。 ADC可以包括混合逐次逼近寄存器（SAR）ADC和斜坡比较ADC。斜坡比较ADC可以通过计数位来控制。在使用SAR ADC和斜坡比较ADC的数据转换之间的转换时，混合ADC可能会受到非理想性的影响。电压偏移可以注入斜坡比较ADC以补偿电压毛刺。斜坡比较ADC可能具有与SAR ADC的最低有效位不足匹配的输出范围。可以向计数位添加纠错位，以增加斜坡比较ADC的输出范围以匹配SAR最低有效位。斜坡比较ADC可以包括增益控制电路，以进一步将输出范围与SAR最低有效位匹配。

8. 发明授权

US07449941B2 Master bias current generating circuit with decreased sensitivity to silicon process variation 有权
标题翻译：主偏置电流产生电路，对硅工艺变化的灵敏度降低
公开(公告)号：US07449941B2
公开(公告)日：2008-11-11
申请号：US11467314
申请日：2006-08-25
申请人： Ali E. Zadeh , Ashirwad Bahukhandi
发明人： Ali E. Zadeh , Ashirwad Bahukhandi
IPC分类号： G05F3/02
CPC分类号： G05F3/30
摘要： A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.
摘要翻译：主偏置电流产生电路包括电流源，第一参考腿和第二参考腿。第一参考支路包括具有耦合到电流源的第一尺寸参数的第一晶体管和具有耦合到第一晶体管的第二尺寸参数的第一二极管。第二参考支路包括具有小于耦合到电流源的第一尺寸参数的第三尺寸参数的第二晶体管，以及具有大于耦合到第二晶体管的第二尺寸参数的第四尺寸参数的第二二极管。

9. 发明申请

US20120287316A1 RAMP AND SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERSION METHODS, SYSTEMS AND APPARATUS 有权
标题翻译： RAMP和后续逼近寄存器模拟数字转换方法，系统和设备
公开(公告)号：US20120287316A1
公开(公告)日：2012-11-15
申请号：US13228502
申请日：2011-09-09
申请人： DONGSOO KIM , Taehee Cho , Isao Takayanagi , Ashirwad Bahukhandi , Chiajen Lee
发明人： DONGSOO KIM , Taehee Cho , Isao Takayanagi , Ashirwad Bahukhandi , Chiajen Lee
IPC分类号： H04N5/335 , H03M1/38 , H03M1/12
CPC分类号： H03M1/122 , H03M1/14 , H03M1/46 , H03M1/56 , H04N5/378
摘要： Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.
摘要翻译：公开了逐次逼近寄存器（SAR）和斜坡模数转换（ADC）方法，系统和装置。通过对模拟电压信号执行SAR转换，通过产生多位数字值的位来将模拟电压信号转换为多位数字值，其中对应于SAR电压电平的位，并产生多个数位值的其他位通过对模拟电压信号执行一个或多个斜坡转换，斜坡转换将模拟电压信号与基于SAR电压电平的电压电平斜坡进行比较。 SAR和斜坡ADC可以使用一个SAR转换和多个斜坡转换来提供多采样。 SAR可以设置多个斜坡转换的第一个斜坡的电压电平，然后可以将其用于在随后的斜坡之前预设电压电平。

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