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1. 发明申请

US20120070975A1 Methods of Forming Gate Structure and Methods of Manufacturing Semiconductor Device Including the Same 有权
标题翻译：形成栅极结构的方法和制造包括其的半导体器件的方法
公开(公告)号：US20120070975A1
公开(公告)日：2012-03-22
申请号：US13228089
申请日：2011-09-08
申请人： Ha-Jin Lim , Moon-Han Park , Min-Woo Song , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Moon-Han Park , Min-Woo Song , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/28
CPC分类号： H01L27/10873 , H01L21/28079 , H01L21/28088 , H01L21/28202 , H01L27/10814 , H01L27/10894 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.
摘要翻译：公开了一种形成具有改善的电特性的玛瑙结构的方法。在基板上形成栅极绝缘层，在栅极绝缘层上形成金属层。然后，通过物理气相沉积（PVD）工艺在金属层上形成非晶硅层。在非晶硅层上形成杂质掺杂多晶硅层。可以防止在非晶硅层和金属层之间的界面处形成氧化物层。

2. 发明授权

US08455345B2 Methods of forming gate structure and methods of manufacturing semiconductor device including the same 有权
标题翻译：形成栅极结构的方法和制造包括其的半导体器件的制造方法
公开(公告)号：US08455345B2
公开(公告)日：2013-06-04
申请号：US13228089
申请日：2011-09-08
申请人： Ha-Jin Lim , Moon-Han Park , Min-Woo Song , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Moon-Han Park , Min-Woo Song , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/28
CPC分类号： H01L27/10873 , H01L21/28079 , H01L21/28088 , H01L21/28202 , H01L27/10814 , H01L27/10894 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming agate structure having an improved electric characteristic is disclosed. A gate insulating layer is formed on a substrate and a metal layer is formed on the gate insulating layer. Then, an amorphous silicon layer is formed on the metal layer by a physical vapor deposition (PVD) process. An impurity doped polysilicon layer is formed on the amorphous silicon layer. Formation of an oxide layer at an interface between the amorphous silicon layer and the metal layer may be prevented.
摘要翻译：公开了一种形成具有改善的电特性的玛瑙结构的方法。在基板上形成栅极绝缘层，在栅极绝缘层上形成金属层。然后，通过物理气相沉积（PVD）工艺在金属层上形成非晶硅层。在非晶硅层上形成杂质掺杂多晶硅层。可以防止在非晶硅层和金属层之间的界面处形成氧化物层。

3. 发明申请

US20120083111A1 Methods of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120083111A1
公开(公告)日：2012-04-05
申请号：US13249505
申请日：2011-09-30
申请人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/32134 , H01L21/32139 , H01L29/517 , H01L29/518
摘要： There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
摘要翻译：提供了制造半导体器件的方法。在该方法中，在基板上形成包括高k电介质材料的栅极绝缘层。在栅绝缘层上形成蚀刻停止层。在蚀刻停止层上形成金属层。在金属层上形成包括非晶硅的硬掩模。使用硬掩模作为蚀刻掩模对金属层进行图案化以形成金属层图案。

4. 发明授权

US08664111B2 Method of patterning a semiconductor device with hard mask 有权
标题翻译：用硬掩模图案化半导体器件的方法
公开(公告)号：US08664111B2
公开(公告)日：2014-03-04
申请号：US13249505
申请日：2011-09-30
申请人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Moon-Han Park , Eun-Gon Kim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/4763
CPC分类号： H01L21/28123 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/32134 , H01L21/32139 , H01L29/517 , H01L29/518
摘要： There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
摘要翻译：提供了制造半导体器件的方法。在该方法中，在基板上形成包括高k电介质材料的栅极绝缘层。在栅绝缘层上形成蚀刻停止层。在蚀刻停止层上形成金属层。在金属层上形成包括非晶硅的硬掩模。使用硬掩模作为蚀刻掩模对金属层进行图案化以形成金属层图案。

5. 发明授权

US08563411B2 Semiconductor devices having a diffusion barrier layer and methods of manufacturing the same 有权
公开(公告)号：US08563411B2
公开(公告)日：2013-10-22
申请号：US13191948
申请日：2011-07-27
申请人： Ha-Jin Lim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/3205
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/4966
摘要： Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

6. 发明申请

US20110306171A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS 审中-公开
标题翻译：用不同绝缘栅绝缘体制作半导体器件的方法
公开(公告)号：US20110306171A1
公开(公告)日：2011-12-15
申请号：US13105652
申请日：2011-05-11
申请人： Ha-Jin Lim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
发明人： Ha-Jin Lim , Jin-Ho Do , Weon-Hong Kim , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/8238 , H01L21/28
CPC分类号： H01L21/823857 , H01L21/28202 , H01L29/518
摘要： An insulation layer is formed on a substrate having an NMOS region and a PMOS region defined therein. A first conductive layer is formed on the insulation layer in the PMOS region, leaving a portion of the insulation layer in the NMOS region exposed. Nitriding is performed to produce a first nitrogen concentration in the insulation layer in the NMOS region and a second nitrogen concentration less than the first nitrogen concentration in the insulation layer in the PMOS region. A second conductive layer is formed on the insulation layer and the first conductive layer and the first and second conductive layers and the insulation layer are patterned to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.
摘要翻译：在其上限定有NMOS区和PMOS区的基板上形成绝缘层。在PMOS区域中的绝缘层上形成第一导电层，使NMOS区域中的绝缘层的一部分露出。进行氮化，以在NMOS区域中的绝缘层中产生第一氮浓度，并且在PMOS区域中的绝缘层中小于第一氮浓度的第二氮浓度。第二导电层形成在绝缘层上，并且第一导电层以及第一和第二导电层和绝缘层被图案化以分别在NMOS区域和PMOS区域中形成第一栅极结构和第二栅极结构。

7. 发明授权

US08673747B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08673747B2
公开(公告)日：2014-03-18
申请号：US13093097
申请日：2011-04-25
申请人： Jin-Ho Do , Ha-Jin Lim , Weon-Hong Kim , Hoi-Sung Chung , Moon-Kyun Song , Dae-Kwon Joo
发明人： Jin-Ho Do , Ha-Jin Lim , Weon-Hong Kim , Hoi-Sung Chung , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/00
CPC分类号： H01L21/02236 , H01L21/02164 , H01L21/022 , H01L21/02238 , H01L21/02271 , H01L21/02532 , H01L21/28194 , H01L21/28211 , H01L29/51 , H01L29/513
摘要： A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.
摘要翻译：制造半导体器件的方法包括：在半导体衬底上形成外延层; 在所述外延层上形成具有第一厚度的覆盖层; 以及在氧气氛中氧化所述覆盖层以形成具有第二厚度的第一栅极介电层。

8. 发明申请

US20110306184A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110306184A1
公开(公告)日：2011-12-15
申请号：US13093097
申请日：2011-04-25
申请人： Jin-Ho Do , Ha-Jin Lim , Weon-Hong Kim , Hoi-Sung Chung , Moon-Kyun Song , Dae-Kwon Joo
发明人： Jin-Ho Do , Ha-Jin Lim , Weon-Hong Kim , Hoi-Sung Chung , Moon-Kyun Song , Dae-Kwon Joo
IPC分类号： H01L21/20
CPC分类号： H01L21/02236 , H01L21/02164 , H01L21/022 , H01L21/02238 , H01L21/02271 , H01L21/02532 , H01L21/28194 , H01L21/28211 , H01L29/51 , H01L29/513
摘要： A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.
摘要翻译：制造半导体器件的方法包括：在半导体衬底上形成外延层; 在所述外延层上形成具有第一厚度的覆盖层; 以及在氧气氛中氧化所述覆盖层以形成具有第二厚度的第一栅极介电层。

9. 发明申请

US20120034752A1 METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成门结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20120034752A1
公开(公告)日：2012-02-09
申请号：US13195521
申请日：2011-08-01
申请人： Weon-Hong KIM , Hyung-Suk Jung , Ha-Jin Lim
发明人： Weon-Hong KIM , Hyung-Suk Jung , Ha-Jin Lim
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L21/28247 , H01L21/823425 , H01L27/10873 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/78
摘要： In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion of the gate electrode. Therefore, a semiconductor device including the gate pattern has excellent electrical characteristics.
摘要翻译：在形成栅极结构的方法中，形成包括依次层叠在基板上的栅极绝缘层图案和栅电极的栅极图案。栅电极包括金属。使用反应气体对栅极图案进行第一等离子体处理，以减少栅电极的氧化边缘部分。反应气体包括氮气。在栅极图案的侧壁上形成间隔物。通过减小栅电极的氧化边缘部分来调节阈值电压。因此，包括栅极图案的半导体器件具有优异的电气特性。

10. 发明授权

US08476155B1 Formation of a high-K crystalline dielectric composition 有权
标题翻译：形成高K结晶介电组合物
公开(公告)号：US08476155B1
公开(公告)日：2013-07-02
申请号：US12835790
申请日：2010-07-14
申请人： Ha-Jin Lim , Weon-Hong Kim
发明人： Ha-Jin Lim , Weon-Hong Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02181 , H01L21/02148 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L21/3105 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Provided are a method of forming a dielectric and a method of fabricating a semiconductor device. The method includes forming a preliminary dielectric including Hf, O and an “A” element on an underlying layer. The preliminary dielectric is formed in an amorphous structure or a mixed structure of an amorphous structure and an “M” crystalline structure. The “A” element about 1 at % to about 5 at % of the total content of the “A” element and Hf in the preliminary dielectric. Through a nitridation process, nitrogen is added to the preliminary dielectric. The nitrogen-containing dielectric is changed into a dielectric having a “T” crystalline structure through a phase transition process, wherein the “T” crystalline structure is different from the “M” crystalline structure. An upper layer is formed on the “T” crystalline dielectric.
摘要翻译：提供形成电介质的方法和制造半导体器件的方法。该方法包括在下层上形成包含Hf，O和“A”元素的预备电介质。预置电介质形成为非晶结构或非晶结构和“M”晶体结构的混合结构。 “A”元素在“A”元素的总含量和预置电介质中的Hf的约1at％至约5at％的“A”元素。通过氮化处理，将氮气加入到初步电介质中。通过相变过程将含氮电介质变成具有“T”晶体结构的电介质，其中“T”晶体结构不同于“M”晶体结构。在“T”晶体电介质上形成上层。

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