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1. 发明申请

WO2002059966A1 PLANARIZERS FOR SPIN ETCH PLANARIZATION OF ELECTRONIC COMPONENTS AND METHODS OF USE THEREOF 审中-公开
标题翻译：用于电子元件的旋转计划平面图的计算机及其使用方法
公开(公告)号：WO2002059966A1
公开(公告)日：2002-08-01
申请号：PCT/US2002/001861
申请日：2002-01-22
申请人： HONEYWELL INTERNATIONAL INC. , MUKHERJEE, Shyama , LEVERT, Joseph , DEBEAR, Donald
发明人： MUKHERJEE, Shyama , LEVERT, Joseph , DEBEAR, Donald
IPC分类号： H01L23/48
CPC分类号： H01L21/32115 , C23F3/06 , H01L21/32134 , H01L21/7684 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An electronic component contemplated comprises a substrate layer (110), a dielectric layer (120) coupled to the substrate layer (110), a barrier layer (130) coupled to the dielectric layer (120), a conductive layer (140) coupled to the barrier layer (130), and a protective layer (150) coupled to the conductive layer (140). A method of making the electronic component comprises the steps of providing a substrate (110) coupling a dielectric layer (120) to the substrate (110), coupling a barrier layer (130) to the dielectric layer (120), coupling a conductive layer (140) to the barrier layer (130), and coupling a protective layer (150) to the conductive layer (140). A method of planarizing a conductive surface of the electronic component comprises the steps of introducing or coupling a protective layer (150) onto a conductive layer (140), dispersing the protective layer (150) across the conductive layer (140), curing the protective layer (150), introducing an etching solution onto the conductive layer (140), and etching the conductive surface to substantial planarity.
摘要翻译：预期的电子部件包括衬底层（110），耦合到衬底层（110）的电介质层（120），耦合到电介质层（120）的阻挡层（130），耦合到所述阻挡层（130）以及耦合到所述导电层（140）的保护层（150）。制造电子部件的方法包括以下步骤：提供将电介质层（120）耦合到衬底（110）的衬底（110），将阻挡层（130）耦合到电介质层（120），将导电层（140）连接到阻挡层（130），并且将保护层（150）耦合到导电层（140）。平面化电子部件的导电表面的方法包括以下步骤：将保护层（150）引入或耦合到导电层（140）上，将保护层（150）分散在导电层（140）上，固化保护层层（150），将蚀刻溶液引入到导电层（140）上，并且将导电表面蚀刻到显着的平面度。

2. 发明申请

WO2002059962A2 VISCOUS PROTECTIVE OVERLAYERS FOR PLANARIZATION OF INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路平面化的VISCOUS保护覆盖层
公开(公告)号：WO2002059962A2
公开(公告)日：2002-08-01
申请号：PCT/US2002/001692
申请日：2002-01-22
申请人： HONEYWELL INTERNATIONAL INC.
发明人： MUKHERJEE, Shyama , DEBEAR, Donald , LEVERT, Joseph
IPC分类号： H01L21/768
CPC分类号： H01L21/32115 , C23F3/06 , H01L21/32134 , H01L21/7684 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10S977/712 , Y10S977/788 , H01L2924/00
摘要： The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.
摘要翻译：本发明涉及通常在集成电路的制造中遇到的表面的平坦化，特别是在镶嵌和双镶嵌互连中遇到的铜导体和Ta / TaN阻挡层。本发明描述了用于Cu / Ta / TaN互连的平坦化方法，其通常利用倾向于驻留在较低表面形貌的区域中的粘性覆层，通过化学和机械效应的组合保护所述下部区域免受蚀刻。在一些实施方案中，粘性覆层包含妨碍从与粘性层接触的表面区域去除铜的物质。这样的物质可以是其他添加剂中基本饱和的铜离子溶液，从而阻碍互连铜溶解到保护性覆盖层中。在本发明的一些实施方案中，可以在将蚀刻剂引入晶片表面之前添加粘性覆层，或者基本上同时引入蚀刻剂和粘性覆盖层，通常当平坦化期间晶片旋转时。

3. 发明公开

EP1354347A2 VISCOUS PROTECTIVE OVERLAYERS FOR PLANARIZATION OF INTEGRATED CIRCUITS 审中-公开
标题翻译： VISKOSE保护涂层关于平面化的使用该组合物制造的集成电路的
公开(公告)号：EP1354347A2
公开(公告)日：2003-10-22
申请号：EP02709115.6
申请日：2002-01-22
申请人： Honeywell International Inc.
发明人： MUKHERJEE, Shyama , DEBEAR, Donald , LEVERT, Joseph
IPC分类号： H01L21/768
CPC分类号： H01L21/32115 , C23F3/06 , H01L21/32134 , H01L21/7684 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10S977/712 , Y10S977/788 , H01L2924/00
摘要： The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer (13) tending to dwell in regions of lower surface topography (8, 9, 10), protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.

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