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1. 发明专利

JPS62197999A EEPROM DEVICE 失效
公开(公告)号：JPS62197999A
公开(公告)日：1987-09-01
申请号：JP3920586
申请日：1986-02-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUAKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To make an operation into high speed by switching the potential of a word line to which an MNOS is coupled to the high voltage of positive/ negative, according to a decode output signal. CONSTITUTION:In a write operation, when a control signal; the inverse of R/W goes to a low level temporarily, a MOSFET Q5 turns to an on-state, then outputting the high voltage like+12V in a high voltage terminal Vpp. Therefore, a MOSFET Q6 is made turn to an off-state, then the high voltage like +12V at the second word line W12, etc., being generated. Therefore, the high voltage like +12V functions between the gate of the MNOS coupled to the second word line W12 and the gate of a base board, and the write operation by the implantation of electric charge based on a tunnel phenomenon is performed.

2. 发明专利

JPH01276500A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01276500A
公开(公告)日：1989-11-07
申请号：JP10516788
申请日：1988-04-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UJIIE KAZUAKI , FURUSAWA KAZUNORI
IPC分类号： G11C17/00 , G11C29/00 , G11C29/34 , H01L21/66 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/112 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To decrease the number of writings and to shorten a test time by providing a circuit to cause the plural word lines of an array, for which a non-volatile memory element to execute electric writing is matrix-arranged, to be simultaneously in a selecting condition with a prescribed test mode signal. CONSTITUTION:An Nch transmitting gate FET Q3 to receive a test signal TE0 is provided for the output of a decoder G of a unit and a Pch transmitting gate FET Q4 to receive the same signal is provided in an output side. An inverter N3 to receive a test signal TE1 is provided in a word line WL of an even number and an inverter to receive a test signal TE2 is provided in a word line WL of an odd number. The outputs of the inverters go to be a decode output through a correspondent Pch transmitting gate FET Q1. Such a test circuit simultaneously selects the plural word lines WL according to the signals TE0-TE2 without depending on the decode output, namely, an address signal. Thus, since much data can be written by one time of the writing, the test time is shortened. When a signal is inputted from a common terminal with being multiplexed, the test signal is held in a latch circuit FF.

3. 发明专利

JPH01117000A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01117000A
公开(公告)日：1989-05-09
申请号：JP27262587
申请日：1987-10-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UJIIE KAZUAKI , NABEYA SHINJI
IPC分类号： G11C29/00 , G11C11/401 , G11C16/06 , G11C17/00 , G11C29/14
摘要： PURPOSE:To increase the number of operating modes without increasing the number of pins by connecting latch circuits which operate at different timing to one input terminal and switching modes according to the combination of signals latched in the respective latch circuits. CONSTITUTION:The latch circuits LT1 and LT2 which operate at mutually different timing are connected to one out-enable signal-OE input terminal and a mode selecting circuit MSC is provided which switches the modes according to the combination of the signals latched by the latch circuits LT1 and LT2. Therefore, when the number of the latch circuits in (n), 2 combinations of signals are obtained and more modes can be set by combining other input signals or connecting latch circuits similarly as to other input signal terminals. Consequently, the number of operation modes can be increased without increasing the number of pins.

4. 发明专利

JPH01166396A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01166396A
公开(公告)日：1989-06-30
申请号：JP32407687
申请日：1987-12-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO NOBUYUKI , NAGAI YOSHIKAZU , UJIIE KAZUAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To prevent the undesired rewriting of data by individually setting an operating mode to fetch the data into a data input latch and an operating mode to rewrite a non-volatile memory cell with the data which are fetched into a data input latch. CONSTITUTION:The operating mode, which can fetch the data into a data input latch DILAT, and the operating mode, which can rewrite a memory cell array MCA by the data to be fetched into the data input latch DILAT, are individually set. Namely, the operating mode, which fetches the data to be supplied from an external part into the data input latch DILAT, is set by the change of a write-enable signal WE to a low level basically. Accordingly, the operating mode, which rewrites the memory cell array MCA by the data to be held by the data input latch DILAT, is enabled only when a write signal WR is caused to be a high level. Thus, the undesired rewriting of the data due to a guiding noise can be prevented.

5. 发明专利

JPS63127495A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63127495A
公开(公告)日：1988-05-31
申请号：JP27186586
申请日：1986-11-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FURUNO TAKESHI , FURUSAWA KAZUNORI , SATO NOBUYUKI , UJIIE KAZUAKI , NAGAI YOSHIKAZU
IPC分类号： G11C17/00 , H03K3/03 , H03K5/13 , H03K5/133 , H03K5/134
摘要： PURPOSE:To stabilize an oscillation circuit utilizing an undermentioned circuit by constituting a signal delay circuit to be built-in in an IC with a resistance element and a capacitor, and increasing the fluctuation of a second resistance element against the process fluctuation of a first resistance element, and changing a current conducted into a second capacitor greatly. CONSTITUTION:Invertor circuits N1-N5, consisting of odd number being cascade-connected in a ring shape, and the delay circuit, installed between them, constitute an oscillation circuit. Namely, the delay circuit, installed between the output of the invertor circuit N1 and the input of the invertor circuit N2, is constituted with a time constant circuit consisting of the first resistor R1 and a first capacitor C1, and with a series circuit, parallel-connected with the capacitor C1 and consisting of a second resistor R2 and a second capacitor C2. At this time, the second resistor R2 ismade to have the large fluctuation than the process fluctuation of the R1, so that the change portion of a charging and discharging current, against the capacitor C1 and due to the change of the resistance value of the resistor R1, is compensated.

6. 发明专利

JPS62197998A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62197998A
公开(公告)日：1987-09-01
申请号：JP3920486
申请日：1986-02-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUAKI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To reduce a current consumption, and to suppress a noise to an another circuit, etc., by increasing a current supplying capacity in the start up time of a voltage generation circuit, and decreasing the current supplying capacity when an output voltage arrives at a prescribed voltage level. CONSTITUTION:When the voltage of a power source voltage Vpp is below than +25V, the output signal LVH of a level detection circuit LVC goes to a low level, therefore, the output of an inverter circuit N1 goes to a high level, and the output signal of frequency F in a ring oscillator circuit OSC is inputted to a voltage generation circuit VPG. At the voltage generation circuit VPG, the power source voltage Vpp having a comparatively large current consumption can be obtained. Meanwhile, when the voltage of the power source voltage Vpp arrives at +25V, the output signal LVH of the level detection circuit LVC goes to the high level, and the oscillation signal of frequency F/4 is inputted to the voltage generation circuit VPG. In this way, at the voltage generation circuit VPG, the power source voltage Vpp having a comparatively small current consumption can be obtained.

7. 发明专利

JPH01162957A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01162957A
公开(公告)日：1989-06-27
申请号：JP32101187
申请日：1987-12-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UJIIE KAZUAKI , TERASAWA MASAAKI , NAGAI YOSHIKAZU , NABEYA SHINJI , MUKODA HIDEFUMI
IPC分类号： G06F12/14 , G06F21/24
摘要： PURPOSE:To secure the protection of secrecy for the stored data by using the cipher codes held by a latch circuit to change a code conversion system. CONSTITUTION:A memory chip contains a cipher latch circuit 12 to hold the cipher codes supplied from outside. At the same time, a code conversion means 10 is added to a data input part together with a code adverse conversion means 11 added to a data output part for adverse conversion of converted codes respectively. Then a code conversion system is changed with use of the cipher codes held by the circuit 12. Therefore it is impossible to obtain the normal data if the ciphers are not available. Then the stored data are protected.

8. 发明专利

JPH01134793A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01134793A
公开(公告)日：1989-05-26
申请号：JP29380787
申请日：1987-11-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UJIIE KAZUAKI , NAGAI YOSHIKAZU , TERASAWA MASAAKI , FURUSAWA KAZUNORI
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To shorten a time necessary for individual rewriting erasing action without deteriorating data holding performance by automatically rewriting and refreshing memory cell data according to internal action for every prescribed timing by which a power source voltage is inputted. CONSTITUTION:The title device has a refreshing action instructing means 16 for activating an address generating means and rewriting means and for instructing the action rewriting a memory cell based on the memory cell data. By the instruction of the refreshing action instructing means 16, the memory cell 1 data are automatically rewritten and refreshed according to the internal action for the prescribed timing by which the power source voltage is inputted. Thus, even when the number of data holding years to be guaranteed by one writing deleting/rewriting action is comparatively short, the memory cell 1 data can be refreshed in a comparatively short cycle such as for every input of the power source voltage, and the time necessary for the individual deleting rewriting action can be shortened without deteriorating the substantial data holding performance.

9. 发明专利

JPH01100788A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01100788A
公开(公告)日：1989-04-19
申请号：JP25787787
申请日：1987-10-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UJIIE KAZUAKI , NABEYA SHINJI
IPC分类号： G11C11/14 , G11C5/14 , G11C16/12 , G11C16/30 , G11C17/18
摘要： PURPOSE:To enable a test by a write voltage lower (higher) than an ordinary voltage to be performed even after sealing a package by connecting a power source voltage terminal and an external terminal to a terminal on which the reference voltage of a limit circuit is applied via two switches. CONSTITUTION:The two switches Q1 and Q2 are connected to the terminal on the reference voltage supplying side of the limit circuit D1 which keeps a booster voltage constant for the voltage set as reference, and the switch Q1 on one side is connected to an internal power source voltage terminal, and also, the switch Q2 on the other side is connected to the external terminal T1 of a chip. In other words, by turning on either the two switches Q1 and Q2 selectively provided at the limit circuit D1, it is possible to perform write by the booster voltage setting an external voltage applied on the external terminal T1 as reference other than the ordinary write by the booster voltage setting the internal power source voltage as reference. In such a way, it is possible to perform the measurement of a margin, a withstand voltage test, and an acceleration test even after sealing the package.

10. 发明专利

JPS5749271A Insulated-gate type field-effect semiconductor device 失效
标题翻译：绝缘栅型场效应半导体器件
公开(公告)号：JPS5749271A
公开(公告)日：1982-03-23
申请号：JP12452080
申请日：1980-09-10
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： UJIIE KAZUAKI , YAMAGUCHI KEN
IPC分类号： H01L29/417 , H01L29/78
CPC分类号： H01L29/42368 , H01L29/78
摘要： PURPOSE:To substantially increase the distance between drain and gate electrodes in order to prevent destruction of a gate oxide film resulting from concentration of field, by gradually increasing the thickness of the gate oxide film from the source to the drain. CONSTITUTION:On a p type Si substrate 10, an SiO2 film 11 and an Si3N4 film 12 are piled up, and an opening 13 is provided in the drain region in order to form an n layer 14. Then, carrying out a thermal oxidation with the Si3N4 12 as a mask permits SiO2 having a gradient film thickness to be obtained. A portion of each of the Si3N4 film 12 and the SiO2 film 11 is removed, the source region is opened in order to provide an n layer 16, and a gate electrode 17 is formed on the gate oxide film 15 between the layers 16 and 14. In this case, the thickness of the gate oxide film 15 is made smaller than the length of the gate between the drain 14 and the source 16. By said constitution, it is possible to ease the concentration of field in the vicinity of the drain junction surface, so that destruction of the gate oxide film.
摘要翻译：目的：为了大大增加漏极和栅电极之间的距离，以便通过逐渐增加栅极氧化膜从源极到漏极的厚度来防止由场强集中引起的栅极氧化膜的破坏。构成：在ap型Si衬底10上堆积SiO 2膜11和Si 3 N 4膜12，在漏极区域设置开口13，以形成n层14.然后，进行热氧化作为掩模的Si 3 N 4 12可以获得具有梯度膜厚度的SiO 2。除去Si 3 N 4膜12和SiO 2膜11中的每一个的一部分，为了提供n层16而打开源极区，并且在层16和14之间的栅极氧化膜15上形成栅电极17 在这种情况下，使栅极氧化膜15的厚度小于漏极14与源极16之间的栅极的长度。通过上述结构，能够使漏极附近的场强集中化接合面，从而破坏栅极氧化膜。

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