专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS62224077A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62224077A
公开(公告)日：1987-10-02
申请号：JP6578086
申请日：1986-03-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG , HITACHI LTD
发明人： KURODA HIDEO , YOSHIDA SEIJI , OKUYAMA KOSUKE , HARA YUJI , SUZUKI CHIKASHI
IPC分类号： H01L29/78
摘要： PURPOSE:To increase the density of integration by forming polycrystalline Si films or high melting-point metallic silicide films, layers thereof mutually differ, which have an area larger than contact holes and to which an impurity is doped, onto a diffusion layer between the mutually adjacent contact holes. CONSTITUTION:A layer insulating film 13 is shaped to the whole surface, and the predetermined sections of the layer insulating film 13 and a gate insulating film 3 to expose the surface of a source region 7. A polycrystalline Si film 14, to which an impurity such as phosphorus is doped and which is connected to the source region 7 and has a large area, is formed. A layer insulating film 9 is shaped to the whole surface, the prescribed sections of the layer insulating film 9 and the layer insulating film 13 are removed through etching to form contact holes 9a, 9b, and wirings 10, 11 are brought into contact with polycrystalline Si films 12, 14 through the contact holes 9a, 9b. Accordingly, the contact holes 9a, 9b can easily be shaped even when an MOSFET is fined, thus increasing the density of integration of an element.

2. 发明专利

JPS62224076A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62224076A
公开(公告)日：1987-10-02
申请号：JP6577586
申请日：1986-03-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： YOSHIDA SEIJI , KATSUTO HISAO , OKUYAMA KOSUKE , HARA YUJI , SUZUKI CHIKASHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L29/78
摘要： PURPOSE:To improve the degree of integration, and to increase mutual conductance by connecting a conductive layer to one surface of S/D regions in an MISFET having LDD structure in a self-alignment manner and constituting the S/D regions, to which the conductive layer is connected or is not connected, only by a high concentration layer. CONSTITUTION:One semiconductor region such as a drain region 5 in reading is formed in LDD structure consisting of a high concentration layer 5A and a low concentration layer 5B, and the other semiconductor region such as a source region 6 on reading is organized only of a high concentration region. Consequently, the resistance values of the semiconductor regions are reduced, thus increasing mutual conductance. A conductive layer 9 on gate electrodes 7 is connected to the drain region 5 on reading in a self-alignment manner, and a data line DL is connected to the conductive layer 9, thus substantially eliminating the need for the mask alignment margin of the data line DL and the drain region 5. Accordingly, the titled device can be fined, and the degree of integration is improved.

3. 发明专利

JPS62224070A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62224070A
公开(公告)日：1987-10-02
申请号：JP6577786
申请日：1986-03-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI CHIKASHI , HARA YUJI , KATSUTO HISAO , OKUYAMA KOSUKE , YOSHIDA SEIJI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE:To reduce a soft-error, and to increase working speed by connecting a data line to an MISFET constituting a circuit conducting the reading operation of informations in a self-alignment manner. CONSTITUTION:A conductive layer 9 consisting of a film such as a polycrystalline silicon film is applied and connected to the surface of an N type semiconductor region 5B as one part of a source or drain region on the side, to which a data line DL is connected, in source or drain regions in four N channel MISFET Qn1-Qn4 to which a sense amplifier SA and the data line DL for a precharge circuit PC are connected. A pattern for a connecting surface between the N type semiconductor region 5B and the conductive layer 9 is specified by each of the end section of a field insulating film 2, the end section of a gate insulating film 4 and a side wall spacer 8. That is, the conductive layer 9 is connected to the N type semiconductor region 5B in a self- alignment manner. Accordingly, a soft-error is reduced, and the reliability of informations can be improved.

4. 发明专利

JPH06349825A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06349825A
公开(公告)日：1994-12-22
申请号：JP14104593
申请日：1993-06-14
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICOM SYST KK
发明人： FUJII TAKAKO , KUBOTA KATSUHIKO , OKUYAMA KOSUKE , SUZUKI CHIKASHI , ISHIDA MOTOKO , YOSHIDA SEIJI , KAWASHIMA YASUHIKO , HISHIKI MASANOBU
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To improve the anti-electromigration of wiring formed on a semiconductor substrate. CONSTITUTION:Slits 10 which have a very narrow width are formed along the extending direction of an Al power supply wiring 8, and the width of the wiring in an area separated by the slit 10 is made the same or less than the average grain diameter of the Al crystal which constitutes the wiring. Thus, the wiring in the area separated by the slits 10 is made to have a bamboo structure.

5. 发明专利

JPS63160244A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63160244A
公开(公告)日：1988-07-04
申请号：JP30646386
申请日：1986-12-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HARA YUJI , OKUYAMA KOSUKE , SUZUKI CHIKASHI , YOSHIDA SEIJI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To suppress the diffusion of heterogenous conductive type impurities into the source and drain of an MISFET by a method wherein a silicon film is provided on the connected surface of a p-type and n-type semiconductor region and a high melting point metal silicide wiring. CONSTITUTION:A polycrystalline silicon film 14 is formed by applying self- alignment in the connection hole 13 wherein a high melting point metal silicide wiring is connected. Then, n-type impurities are formed by implanting ions in the film 14 in the connection hole 13 of n type and n-type semiconductor regions 8 and 9. The impurities of p-type are formed on the film 14 in the connection hole of a p type semiconductor region 10 in the same manner as above-mentioned. Then, a high melting point metal film or its silicide film is formed on the whole surface of a substrate 1, and a high melting point metal silicide wiring 15 is formed by patterning. As a result, the distance between a polycrystalline silicon film and a source and drain is increased, the diffusion of impurities is decreased, and the reliability of the title device can be improved.

6. 发明专利

JPS6379372A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6379372A
公开(公告)日：1988-04-09
申请号：JP22357186
申请日：1986-09-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： YOSHIDA SEIJI , SUZUKI CHIKASHI
IPC分类号： G11C11/41 , H01L27/10 , H01L27/11
摘要： PURPOSE:To implement high integration density and low electric power and to improve a data holding characteristic, by constituting the FF circuit of a memory cell by driving MISFETs, gate electrodes in drain regions of the FETs and JFETs for loads in said regions. CONSTITUTION:The FF circuit of a memory cell is composed of driving MISFET Qds, gate electrodes 5, which are formed with drain regions 6 of said FETs Qds, and JFETs Qjs for loads having channel regions 7, which are formed in the drain regions. Thus, the supply of a power source voltage Vcc can be controlled with the JFETs for the loads. Therefore, power consumption is decreased and the data holding characteristic can be improved. A part of each JFETQj for the load can be formed in the occupying area of the region 6 of the driving MISFET Qd. Therefore, the area of the memory cell is reduced, and the integration density can be improved.

7. 发明专利

JPS6354772A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6354772A
公开(公告)日：1988-03-09
申请号：JP19718186
申请日：1986-08-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI CHIKASHI , OKUYAMA KOSUKE , YOSHIDA SEIJI
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10
摘要： PURPOSE:To reduce a short channel effect thereby to improve the electric characteristics of a MISFET by providing a reverse conductivity type semicon ductor region to source and drain regions between a part separated from the channel region of the source, drain regions and the channel region. CONSTITUTION:A first semiconductor region 8 for forming a part separated from the channel region 10 of source, drain regions at both sides of a gate electrode 5 and a reverse conductivity type second semiconductor region 6 to the source and drain regions 8 provided between the first semiconductor region 8 and the channel region 10 of the surface of a semiconductor substrate 1 are provided in a MISFET. Further, a pair of third semiconductor regions 7 provided around the second semiconductor region 6 for forming the channel region 10 of the source and drain region 8 and a pair of reverse conductivity type fourth semiconductor regions 9 to the source and drain regions 8 provided around the third region 7 are provided. Thus, since the extension of the deple tion region is reduced, short channel effect is reduced to improve the electric characteristics.

8. 发明专利

JPS62274741A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62274741A
公开(公告)日：1987-11-28
申请号：JP11737586
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HARA YUJI , OKUYAMA KOSUKE , SUZUKI CHIKASHI , KATSUTO HISAO , YOSHIDA SEIJI
IPC分类号： H01L21/76
摘要： PURPOSE:To securely but easily form a channel stopper region in the semiconductor substrate on the side wall part of a groove by a method wherein impurities are diffused in the semiconductor substrate from the film constituting the impurity diffusion source formed on the side wall of a groove. CONSTITUTION:By performing an etching operation on a boron-silicate glass (BSG) film 5 using a photoresist film 6 as a mask, the part of the BSG film 5 corresponding to a p-well 3 is left, and then said photoresist film 6 is removed. Then, the boron in the BSG film 5 is diffused into a semiconductor substrate 1 by performing a heat treatment, and a p-type channel stopper region 7, having the impurity density higher than that of the p-well 3, is formed in the semiconductor substrate 1 on the bottom part and the side wall part of the grooves 1b and 1c located in the p-well. As a result, the channel stopper region 7 is securely but easily formed not only on the bottom part of the grooves 1b and 1c but also on the side wall part of the grooves 1b and 1c.

9. 发明专利

JPS6265453A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6265453A
公开(公告)日：1987-03-24
申请号：JP20429685
申请日：1985-09-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SUZUKI CHIKASHI , OGISHIMA JUNJI , ARAKAWA YUSHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
摘要： PURPOSE:To improve the degree of integration, and to enhance the holding characteristics of information by forming capacity electrodes as being divided at every memory cell while applying predetermined potential by wirings for feed connected to the upper surfaces of the capacity electrodes. CONSTITUTION:A dielectric film 2 for a capacity element, a p-type semiconductor region 4A and an n type semiconductor region 5A are shaped to the surfacer of a substrate 1. A polycrystalline silicon film 6 is formed on the whole surface on the substrate 1, and patterned into a pattern in which two bits are unified by using resist marks 7. The exposed dielectric film 2 and the substrate 1 are etched, and grooves 8 are shaped. p-type channel stopper regions 9 are formed on the surfaces of the substrates 1 in the bottoms of the grooves 8, and silicon oxide films 10 are buried into the grooves 8 and shaped on the whole surfaces on the substrates 1. Element isolation insulating films 10A are formed through etching from upper surfaces. A polycrystalline silicon film 11 and a resist mask 12 having a pattern in which regions in which MISFETs are shaped are exposed are formed on the whole surface on the substrate 1, and the polycrystalline silicon film 11 is etched, thus completing wirings for feed.

10. 发明专利

JPS63136674A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63136674A
公开(公告)日：1988-06-08
申请号：JP28174686
申请日：1986-11-28
申请人： HITACHI LTD
发明人： SUZUKI CHIKASHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To eliminate the need for performing mask alignment between an element isolation insulating film and a MISFET and not only reduce an element isolation region but enhance integration by prescribing a region of the element isolation insulating film in accordance with a gate electrode of the MISFET. CONSTITUTION:A pattern of an element isolation insulating film 2 is prescribed by the pattern which is formed by the first time patterning of a polycrystal silicon film that turns into floating gate electrodes 5 formed on the semiconductor substrate 1. Therefore, end parts contacting side faces of the floating electrodes 5 of the element isolation insulating film 2 are prescribed by the floating gate electrode 5. Then, no mask alignment is needed between the floating gate electrodes 5 and the element isolation insulating film 2. As a result, a distance between floating gate electrodes 5 that are adjacent to each other in the direction of the extension of work lines WL can be reduced. A region equipped with the element isolation insulating film 2 can reduce its element isolation insulating film 2 by having a structure where no etching is required. What's more, a p-channel stopper region 3 with the pattern that is identical to that of the above insulating film 2 is formed below the element isolation insulating film 2.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式