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1. 发明专利

JPH10149696A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10149696A
公开(公告)日：1998-06-02
申请号：JP32388797
申请日：1997-11-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KURODA KENICHI , TAKEDA TOSHIFUMI , MORIUCHI HISAHIRO , SHIRAI MASAKI , SAKAGUCHI JIRO , MATSUO AKINORI , YOSHIDA SEIJI
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a circuit which is improved in data retention characteristics, capable of relieving faults, changing functions or trimming owing to easy manufacturing and high reliability by providing a barrier layer covering the floating gate partially or wholy in a non-volatile memory element of single-layer gate structure. SOLUTION: The memory mat MR-MAT is provided with memory elements for mask ROM in the form of matrix. The memory mat PR-MAT is provided with a matrix of single-layer gate structured non-volatile memory elements for relieving defective data. The word line of the memory mat MR-MAT is selected by an X decoder circuit XDC. The data line of the memory mat MR- MAT is connected to the common data line by a column switch gate MR-YGT. The column switch gate MR-YGT operates to connect one data line for each output mat from the inside of the memory mat MR-MAT to the common data line.

2. 发明专利

JPS6421971A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6421971A
公开(公告)日：1989-01-25
申请号：JP17846487
申请日：1987-07-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKUYAMA KOSUKE , NAGAI AKIRA , YOSHIDA SEIJI
IPC分类号： H01L27/112 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a memory cell of a structure, wherein the memory cell can be formed in less manufacturing processes, by a method wherein a control gate electrode is constituted of the semiconductor region of the surface of a substrate and a floating gate electrode is constituted of first-layer conductor layers provided ranging from the upper part of at least the control gate electrode to the upper part of the channel region of a MISFET. CONSTITUTION:The writing of information is performed by infecting a charge in a floating gate electrode of a MISFET having the floating gate electrode and a control gate electrode and for information storage. In such a semiconductor integrated circuit device, the control gate electrode CG is constituted of the semiconductor region of the surface of a substrate 1 and the floating gate electrode FG is constituted of first-layer conductor layers 7 and 8 provided ranging from the upper part of at least the above electrode CG to the upper part of a channel region of the MISFET. Thereby, as the conducting layers, which are formed on the substrate 1 for constituting a memory cell, result in being used as layers for forming only the electrode FG and gate electrodes SE for selection, the memory cell, which can be formed in less manufacturing processes, can be obtained.

3. 发明专利

JPS62224077A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62224077A
公开(公告)日：1987-10-02
申请号：JP6578086
申请日：1986-03-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG , HITACHI LTD
发明人： KURODA HIDEO , YOSHIDA SEIJI , OKUYAMA KOSUKE , HARA YUJI , SUZUKI CHIKASHI
IPC分类号： H01L29/78
摘要： PURPOSE:To increase the density of integration by forming polycrystalline Si films or high melting-point metallic silicide films, layers thereof mutually differ, which have an area larger than contact holes and to which an impurity is doped, onto a diffusion layer between the mutually adjacent contact holes. CONSTITUTION:A layer insulating film 13 is shaped to the whole surface, and the predetermined sections of the layer insulating film 13 and a gate insulating film 3 to expose the surface of a source region 7. A polycrystalline Si film 14, to which an impurity such as phosphorus is doped and which is connected to the source region 7 and has a large area, is formed. A layer insulating film 9 is shaped to the whole surface, the prescribed sections of the layer insulating film 9 and the layer insulating film 13 are removed through etching to form contact holes 9a, 9b, and wirings 10, 11 are brought into contact with polycrystalline Si films 12, 14 through the contact holes 9a, 9b. Accordingly, the contact holes 9a, 9b can easily be shaped even when an MOSFET is fined, thus increasing the density of integration of an element.

4. 发明专利

JPH06267977A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06267977A
公开(公告)日：1994-09-22
申请号：JP5167493
申请日：1993-03-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ARIGA SEIICHI , MATSUDA NOZOMI , YOSHIDA SEIJI , MORI CHIEMI , TOYOKAWA SHIGEYA , IWANAGA TAIJI , KUNIMOTO YUKINORI
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/784
摘要： PURPOSE:To improve an electric characteristic of a MISFET by reducing resistance of a diffusion layer directly under a contact hole and a contact resistance between this diffusion layer and a conductive layer. CONSTITUTION:Prior to a process of forming a contact hole by opening an insulating film 3 between the gates 2, 2 of a pair of a MISFET formed on a semiconductor substrate 1, ion implantation is performed on the semiconductor substrate 1 in the contact hole forming region from the direction to be slanting being seen from a section of a semiconductor substrate 1 along the extending direction of the gate electrode 2 and to be vertical being seen from the section of the semiconductor substrate 1 along the direction orthogonal to the extending direction of the gate electrode 2. Next, after the contact hole is formed, a conductive layer is formed on the upper part of the MISFET in order to electrically connect the conductive layer to a diffusion layer 4 directly under the contact hole through the contact hole.

5. 发明专利

JPH06252169A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING THEREOF 失效
公开(公告)号：JPH06252169A
公开(公告)日：1994-09-09
申请号：JP3186193
申请日：1993-02-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA SEIJI , TOYOKAWA SHIGEYA , MATSUDA NOZOMI , ARIGA SEIICHI , MORI CHIEMI , IWANAGA TAIJI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/784
摘要： PURPOSE:To make it possible to form a channel region, a source region, and a drain region with self-alignment without using a host mask by depositing a semiconductor layer on a gate electrode and on a main surface through an insulation film and etching back the semiconductor layer until the gate insulation film is exposed. CONSTITUTION:In a semiconductor device of a lower section gate structure where a gate electrode 13 is formed on the insulating main surface 12, the gate electrode 13 is formed on the insulating main surface 12 of a substrate 11, and the gate electrode 13 is covered with a gate insulation film 14 to form first semiconductor layer 15 on the upper gate electrode 13 and on the upper section of the main surface 12 through the insulation film 14. Further, the first semiconductor layer 15 on the gate insulation film 14 positioned on the upper section of the gate electrode 13 is removed to form a source region 15a and a drain 15b are formed on both ends of the gate electrode 13. Furthermore, a second semiconductor layer 16 to serve as an opposite conductivity type channel region with respect to the first semiconductor layer 15 is formed on the insulation film 14 on the upper section of the gate electrode 14 and on the first semiconductor layer 15.

6. 发明专利

JPS62224076A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62224076A
公开(公告)日：1987-10-02
申请号：JP6577586
申请日：1986-03-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： YOSHIDA SEIJI , KATSUTO HISAO , OKUYAMA KOSUKE , HARA YUJI , SUZUKI CHIKASHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L29/78
摘要： PURPOSE:To improve the degree of integration, and to increase mutual conductance by connecting a conductive layer to one surface of S/D regions in an MISFET having LDD structure in a self-alignment manner and constituting the S/D regions, to which the conductive layer is connected or is not connected, only by a high concentration layer. CONSTITUTION:One semiconductor region such as a drain region 5 in reading is formed in LDD structure consisting of a high concentration layer 5A and a low concentration layer 5B, and the other semiconductor region such as a source region 6 on reading is organized only of a high concentration region. Consequently, the resistance values of the semiconductor regions are reduced, thus increasing mutual conductance. A conductive layer 9 on gate electrodes 7 is connected to the drain region 5 on reading in a self-alignment manner, and a data line DL is connected to the conductive layer 9, thus substantially eliminating the need for the mask alignment margin of the data line DL and the drain region 5. Accordingly, the titled device can be fined, and the degree of integration is improved.

7. 发明专利

JPS62224070A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62224070A
公开(公告)日：1987-10-02
申请号：JP6577786
申请日：1986-03-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI CHIKASHI , HARA YUJI , KATSUTO HISAO , OKUYAMA KOSUKE , YOSHIDA SEIJI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE:To reduce a soft-error, and to increase working speed by connecting a data line to an MISFET constituting a circuit conducting the reading operation of informations in a self-alignment manner. CONSTITUTION:A conductive layer 9 consisting of a film such as a polycrystalline silicon film is applied and connected to the surface of an N type semiconductor region 5B as one part of a source or drain region on the side, to which a data line DL is connected, in source or drain regions in four N channel MISFET Qn1-Qn4 to which a sense amplifier SA and the data line DL for a precharge circuit PC are connected. A pattern for a connecting surface between the N type semiconductor region 5B and the conductive layer 9 is specified by each of the end section of a field insulating film 2, the end section of a gate insulating film 4 and a side wall spacer 8. That is, the conductive layer 9 is connected to the N type semiconductor region 5B in a self- alignment manner. Accordingly, a soft-error is reduced, and the reliability of informations can be improved.

8. 发明专利

JPH07153300A NON-VOLATILE MEMORY AND ITS SCREENING METHOD 失效
公开(公告)号：JPH07153300A
公开(公告)日：1995-06-16
申请号：JP29766093
申请日：1993-11-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA SEIJI , OKUYAMA KOSUKE , KOMORI KAZUHIRO , WADA MASASHI , FURUNO TAKESHI
IPC分类号： G01R31/26 , G01R31/28 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/06 , G11C29/56 , H01L21/8247 , H01L27/115
摘要： PURPOSE:To obtain a non-volatile memory which can reduce market defective rate. CONSTITUTION:This memory is provided with a non-volatile memory section 1 in which plural memory cells are arranged, a data read-out circuit 2, writing voltage/pulse generating circuit 3, and erasing voltage/pulse generating circuit 4, the data readout circuit 2 and the writing voltage/pulse generating circuit 3 and the erasing voltage/pulse generating circuit 4 are respectively connected to an operation power supply Vcc and operation power supply Vpp. A voltage switching signal S1 is provided in the writing voltage/pulse generating circuit 3 and the erasing voltage/pulse generating circuit 4, by externally operating the voltage switching signal S1, values of writing voltage/pulse and erasing voltage/pulse supplied to the nonvolatile memory section 1 from the writing voltage/pulse generating circuit 3 and the erasing voltage/pulse generating circuit 4 is set valuably independently of the operation power supply VPP.

9. 发明专利

JPS6467938A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6467938A
公开(公告)日：1989-03-14
申请号：JP22396387
申请日：1987-09-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA SEIJI
IPC分类号： H01L21/316 , H01L21/76
摘要： PURPOSE:To prevent crystal defects from generating in a semiconductor substrate near the end of a field insulating film at the time of thermal oxidation by thermally oxidizing it in an oxidative atmosphere containing at least phosphorus. CONSTITUTION:An SiO2 film 2, an Si3N4 film 3 are sequentially formed on a semiconductor substrate 1, the films 3, 2 are then sequentially etched to form an opening 4. Then, an Si3N4 film 5 and an SiO2 film 6 are sequentially formed on a whole surface. Thereafter, the insulating films 6, 5 are sequentially anisotropically etched to remain only on the sidewall of the opening 4, and with them as masks the substrate 1 is anisotropically etched to form a groove 1a. Then, with the films 3, 6 as oxide preventive films the substrate 1 is thermally oxidized in an oxidative atmosphere containing P. The formed field insulating film is formed of glass containing phosphorus, has a low melting point, a large fluidity, and alleviates a stress generated in the substrate near the end of the film, thereby preventing crystal defects from generating.

10. 发明专利

JPS63160244A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63160244A
公开(公告)日：1988-07-04
申请号：JP30646386
申请日：1986-12-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HARA YUJI , OKUYAMA KOSUKE , SUZUKI CHIKASHI , YOSHIDA SEIJI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To suppress the diffusion of heterogenous conductive type impurities into the source and drain of an MISFET by a method wherein a silicon film is provided on the connected surface of a p-type and n-type semiconductor region and a high melting point metal silicide wiring. CONSTITUTION:A polycrystalline silicon film 14 is formed by applying self- alignment in the connection hole 13 wherein a high melting point metal silicide wiring is connected. Then, n-type impurities are formed by implanting ions in the film 14 in the connection hole 13 of n type and n-type semiconductor regions 8 and 9. The impurities of p-type are formed on the film 14 in the connection hole of a p type semiconductor region 10 in the same manner as above-mentioned. Then, a high melting point metal film or its silicide film is formed on the whole surface of a substrate 1, and a high melting point metal silicide wiring 15 is formed by patterning. As a result, the distance between a polycrystalline silicon film and a source and drain is increased, the diffusion of impurities is decreased, and the reliability of the title device can be improved.

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