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1. 发明专利

JPS62210661A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62210661A
公开(公告)日：1987-09-16
申请号：JP5252786
申请日：1986-03-12
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： OKANO KUMIKO , MASUDA MASACHIKA
IPC分类号： H01L27/10 , H01L21/822 , H01L27/00 , H01L27/04
摘要： PURPOSE:To improve the packaging density of a device, by providing a power- source noise decreasing member in a semiconductor chip package. CONSTITUTION:A semiconductor chip 2 is fixed on a tab 1, for which a lead frame is a starting constitution. On the semiconductor chip 2, a power-source- noise decreasing member 4 comprising a bypass capacitor is provided through a protruded electrode 3 comprising a solder bump and the like. One terminal of the member 4 is electrically connected to one terminal of the power source of the semiconductor chip 2 through the protruded electrode 3. The other terminal is electrically connected to a lead 6 through the other terminal of the power source of the semiconductor chip 2 and a bonding wire 5. Even if the power- source noise decreasing member 4 is provided on the semiconductor chip 2, the dimensions of a package is not changed, and the packaging density of the semiconductor device can be improved.

2. 发明专利

JPH04111386A ELECTRONIC DEVICE 失效
公开(公告)号：JPH04111386A
公开(公告)日：1992-04-13
申请号：JP22930890
申请日：1990-08-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TERADA KAZUHIRO , OTSUKA KENICHI , KIMOTO RYOSUKE , MASUDA MASACHIKA , SUGANO TOSHIO , AKEYAMA KENJI , MURAKAMI HAJIME , NISHIMURA ASAO , KITANO MAKOTO
IPC分类号： H05K1/18 , H05K1/00 , H05K1/02 , H05K1/03 , H05K3/34 , H05K3/46
摘要： PURPOSE:To ensure the reliability of a soldered part at a module on which many IC's have been mounted by a method wherein a board whose coefficient of thermal expansion is matched to the value of an IC package as far as possible is used. CONSTITUTION:At an electronic device, a single-layer board or a multilayer board, of ten layers or lower, whose coefficient of thermal expansion is at 7.0X10 to 3.0X10 is used, and a semiconductor device in a package in which an interval between opposite lead terminals is at 10mm or higher and the height of leads from the board is at 0.7mm or lower is mounted at least on one face. Leads 3 of a TSOP- type semiconductor device 2 on a ceramic board 1 are bonded (soldered) by using a solder 4 and the device is mounted. The thickness of the package for the TSOP-type semiconductor device 2 is at about 1.27mm. The ceramic board 1 has a multilayer interconnection structure formed in the following manner: copper foils 1B having a thickness of about 18mum are pasted on both faces of a ceramic core material 1; glass cloths are impregnated with an epoxy resin and dried to form prepregs 1C; the prepregs having a thickness of about 100mum are laminated on the copper foils; copper foils 1B having a thickness of about 18mum are pasted on them; prepregs 1C having a thickness of about 100mum are laminated on them; the copper foils 1B having a thickness about 18mum are pasted on them.

3. 发明专利

JPS63126257A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63126257A
公开(公告)日：1988-05-30
申请号：JP27184686
申请日：1986-11-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAGIWARA YASUHISA , MORITA TOSHIYA , MASUDA MASACHIKA
IPC分类号： H01L23/50 , H01L21/60
摘要： PURPOSE:To prevent short-circuit of bonding wires, by providing means for preventing short circuit of bonding wires and giving a certain degree of freedom to the positional relation between a lead frame and pads on a semiconductor chip. CONSTITUTION:A tip end of a lead 15A corresponding to a corner of a tab 13 is branched to several sections. The leads 15A and lead 15B on the opposite sides of a tab hanging lead 14 are spaced from the lead 14 by a distance D1 that is larger than a distance D2 between other lead 15 and the lead 15A or 15B. Each pad 12A on a semiconductor chip 12 can be electrically connected to an appropriate lead by means of a bonding wire 17, by selecting a lead whose tip end is located at a position closest to the tip end of the lead 15A and not contacted with the lead 14. Accordingly, short-circuit of the bonding wires 17 can be prevented completely.

4. 发明专利

JPS6298753A RESIN-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6298753A
公开(公告)日：1987-05-08
申请号：JP23743485
申请日：1985-10-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKAMOTO MICHIO , MASUDA MASACHIKA , HAGIWARA YASUHISA , MATSUZAWA ASAO
IPC分类号： H01L23/28 , H01L23/31
摘要： PURPOSE:To shorten the length of the wires to be used for electrical connection by mounting a semiconductor pellet on the pellet attaching substrate whose pellet attaching surface is lower than the wiring forming surface. CONSTITUTION:A semiconductor pellet 3 is sealed in a packaging resin 1 along with a pellet attaching substrate 5 to which the pellet is being bonded through such a bonding agent 4 as a silver paste. The pellet attaching substrate 5 consists of a glass epoxy substrate, its peripheral upper surface is a wiring forming surface and a pellet attaching surface is formed at its central part at the position lower than the wiring forming surface. That is, the pellet attaching surface is formed as the bottom surface of the recessed part surrounded with the wiring forming surface in all directions. By this way, the length of wires can be shortened because a wiring layer 6 is allowed to approach the pellet 3 and moreover, as the wiring layer can be formed in a desired form, a bonding area of sufficient width can be ensured.

5. 发明专利

JPS6281738A LEAD FRAME AND SEMICONDUCTOR DEVICE USING SAID LEAD FRAME 失效
公开(公告)号：JPS6281738A
公开(公告)日：1987-04-15
申请号：JP22183285
申请日：1985-10-07
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： HAGIWARA YASUHISA , MASUDA MASACHIKA
IPC分类号： H01L23/50 , H01L21/48 , H01L23/495
摘要： PURPOSE:To ensure bonding and to prevent short circuits of wires, by the structure of a lead frame, which is formed so that the width of an inner lead that is provided at the neighborhood of a tab suspending lead is larger than other inner leads. CONSTITUTION:A lead frame 1 has a square frame part 2, a plurality of leads, which are extended to the central direction from each side of the frame part 2, and tie bars 4, which connect the intermediate parts of the leads. At the central part of the lead frame 1, a square tab 5 is formed. The tab 5 is supported with suspending leads 6, which link the four corners of the tab 5 and the four corners of the frame part 2. Each part of the lead 3 surrounded by the tie bar 4 forms an inner lead 7. The surface of at least tip part of the inner lead 7 is plated with a gold layer and the like for excellent bonding. The width of an inner lead 7a neighboring the tab suspending lead is made broader than the width of other inner lead 7.

6. 发明专利

JPS60113997A TRAY FOR CONVEYING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60113997A
公开(公告)日：1985-06-20
申请号：JP22066583
申请日：1983-11-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MASUDA MASACHIKA , NARISAWA AKIHIKO , HAYASHI MAKOTO , KURIMOTO MORIAKI
IPC分类号： B65D85/86 , B65D85/38 , H05K13/00

7. 发明专利

JPH02192150A RESIN-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02192150A
公开(公告)日：1990-07-27
申请号：JP976589
申请日：1989-01-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICROCUMPUTER ENG
发明人： WADA TAMAKI , MASUDA MASACHIKA , OKANO KUMIKO
IPC分类号： H01L23/28 , H01L23/50
摘要： PURPOSE:To reduce a heat resistance and to prevent the bent of inner leads due to the flow of a resin at the time of resin sealing by a method wherein the plate thicknesses of the inner lead parts of a lead frame are made thicker than those of the outer lead parts of the frame. CONSTITUTION:A semiconductor chip 3 is connected electrically with inner lead parts 5 of a lead frame 1 by wires 4 for connector use, outer lead parts 7 of the frame 1 are exposed outside of a resin sealed body 6 and the parts 7 are bent to the base of the body 6. In this case, the plate thicknesses of the parts 5 are constituted thicker than those of the parts 7. Thereby, the contact areas of the parts 5 with the body 6 are increased, heat which is generated in a package is easily dissipated and a heat resistance can be reduced. Moreover, the bent of the inner leads due to the flow of a resin at the time of transfer molding is also decreased.

8. 发明专利

JPS62210658A RESIN SEALED TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62210658A
公开(公告)日：1987-09-16
申请号：JP5252686
申请日：1986-03-12
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MASUDA MASACHIKA , OKANO KUMIKO
IPC分类号： H01L23/50 , H01L21/48 , H01L23/28
摘要： PURPOSE:To obtain a resin packaged type semiconductor device characterized by high packaging reliability, by providing dimples having an inverted taper structure, in which a coaxial shape is provided, the thinning angle becomes smaller toward the inside and plurality of steps are provided, in the surface of a tab by a plurality of pressing processes. CONSTITUTION:Many dimples 9 are formed at the central part of a metal plate 10, i.e., a part where a tab 5 and an inner lead 4a are formed by press work. The dimples are formed through two pressing processes. At the first press work, a wedge shaped metal tool 11, which has a relatively broad taper angle, is pressed to the specified position of the metal plate 10. Then, the second pressing process is performed by a wedge metal tool 12, whose taper angle is relatively narrow. Each dimple 9 formed in this way has a two-step structure, which has the inverse taper surface formed by the wedge shaped metal tool 11 having the large taper angle, and inverse taper surface formed by the wedge shaped metal tool 12 having the small taper angle. Warping is not yielded in the frame material at the time of the pressing, and the structure of the deep dimples 9 can be obtained.

9. 发明专利

JPS6329960A LEAD FRAME FOR RESIN SEAL TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6329960A
公开(公告)日：1988-02-08
申请号：JP17167786
申请日：1986-07-23
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： HAGIWARA YASUHISA , KIMOTO RYOSUKE , NISHIDA TAKAFUMI , MASUDA MASACHIKA
IPC分类号： H01L23/50
摘要： PURPOSE:To prevent interfacial peeling between a resin and a lead frame, to obviate the generation of resin cracks and to improve packaging properties by projecting a projecting section from the corner section of a tab section and forming a through-hole to the projecting section. CONSTITUTION:Projecting sections 3 projecting to the outside of a tab section 1, with which a semiconductor chip 11 is joined, are protruded to the corner sections of the tab section 1, and through-holes 4 vertically penetrating the projecting sections 3 are bored to the projecting sections 3 as required. The projecting sections 3 are also projected to the corner sections of the tab section 1 aiming at a fact that connecting sections with tab hanging leads 2 in the tab section 1 are hardly peeled generally from a resin. Accordingly, peeling from the resin is reduced, and resin cracks are difficult to be shaped even when a surface package type semiconductor package is packaged by soldering, thus elevating a packaging temperature, then improving packaging properties.

10. 发明授权

US6285074B2 Semiconductor device 有权
公开(公告)号：US6285074B2
公开(公告)日：2001-09-04
申请号：US76157201
申请日：2001-01-18
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUGIYAMA MICHIAKI , WADA TAMAKI , MASUDA MASACHIKA
IPC分类号： H01L23/28 , H01L21/60 , H01L23/495 , H01L23/50
CPC分类号： H01L24/06 , H01L23/4951 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/4899 , H01L2224/49171 , H01L2224/73215 , H01L2224/85201 , H01L2224/85205 , H01L2924/00014 , H01L2924/00015 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01039 , H01L2924/01074 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2224/451 , H01L2924/00 , H01L2924/00012
摘要： In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission.Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package.Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

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