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1. 发明专利

JPH01119828A MICROPROCESSOR 失效
公开(公告)号：JPH01119828A
公开(公告)日：1989-05-11
申请号：JP27741087
申请日：1987-11-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： NOGUCHI YOSHIKI , TSUCHIYA FUMIO , TSUKAMOTO TAKU , MASUMURA SHIGEKI , NAKAMURA HIDEO , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
摘要： PURPOSE:To improve the code efficiency by constructing an instruction system of a microprocessor in a byte unit in which an address operation and an operand operation of an operand are orthogonal to each other. CONSTITUTION:When an address is supplied from a microprocessor, read-out and write of a data are executed through data buses 16, 17 and among the data which are supplied through the data bus H17, an instruction code is sent to an instruction register 10 through prefetch registered 18, 19 in which a prefetched instruction code is stored, and a data for executing an arithmetic processing is inputted to an arithmetic circuit 4. The instruction code is further sent from the instruction register 10 to indirect registers 11-14 for holding an instruction data and a part of the instruction code in the course of executing an instruction. An instruction decoder 1 outputs its address to a microprogram store memory 5.

2. 发明专利

JPS63163658A INFORMATION PROCESSOR 失效
公开(公告)号：JPS63163658A
公开(公告)日：1988-07-07
申请号：JP30850786
申请日：1986-12-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKANO MAKOTO , KURAKAZU KEIICHI , HOSHI YASUHIKO , BABA SHIRO
IPC分类号： G06F13/42 , G06F9/30 , G06F12/00
摘要： PURPOSE:To secure the pre-charge period of a dynamic type RAM and to surely perform the delivery of a bus master right keeping high speed by making a clock signal into a high frequency, by attaching a function which inserts a weight clock of one or plural clocks selectively, at the beginning or the end of a machine cycle consisting of plural clocks. CONSTITUTION:A weight control circuit WT is provided, and the weight control circuit WT is made to have the function which inserts a weight clock signal selectively to the machine cycle consisting of plural clock signals, according to a control signal formed corresponding to a prescribed instruction or operating state. In other words, the weight is provided for an asynchronous data transfer operation, and it is inserted when, as the machine cycle T2, a data transfer completion signal DTACK is not returned until the start time of a state S5. In such way, it is possible to secure the pre-charge period of the dynamic RAM, or to surely perform the delivery of the bus master right.

3. 发明专利

JPS6353662A ADDRESS DECISION CIRCUIT 失效
公开(公告)号：JPS6353662A
公开(公告)日：1988-03-07
申请号：JP19545986
申请日：1986-08-22
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： HOSHI YASUHIKO , TAKANO MAKOTO , BABA SHIRO , KURAKAZU KEIICHI
IPC分类号： G06F12/06 , G06F12/16
摘要： PURPOSE:To immediately decide the error arising when a CPU specifies an address by allocating a corresponding address space to a packaged memory. CONSTITUTION:When the CPU transmits an address signal A defined by a basic address A1 and an area length B1, an address decision circuit DEC activates a selection signal CS1, and brings a memory device ML into a selection state. There is a case where an address space packaged with nothing lies on a memory map in order to allocate address spaces to memory devices M1-M3 and an I/O device. When the CPU specifies an address for undefined address space, the circuit DEC can immediately decide the specification from a set basic address and its area length. The error signal ERP is transmitted to the CPU, which executes a prescribed error processing program through internal interruption.

4. 发明专利

JPS6419445A DATA STORAGE SYSTEM 失效
公开(公告)号：JPS6419445A
公开(公告)日：1989-01-23
申请号：JP17470987
申请日：1987-07-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKANO MAKOTO , HOSHI YASUHIKO , KURAKAZU KEIICHI , BABA SHIRO
IPC分类号： G06F12/08 , G06F12/02 , G06F12/04 , G06F13/00
摘要： PURPOSE:To improve the memory use efficiency and to shorten the data read time by preventing the occurrence of an ineffective buffer area which is left unused and only taking one descriptor to obtain the leading address of a buffer area where desired data is stored. CONSTITUTION:A leading address TA of the buffer area where reception data of one frame is stored is described in a first pointer PNT1 of a descriptor DD1, and a leading address DTA of the memory area where a descriptor DD2 following the descriptor DD1 is stored is described in a second pointer PNT2. Each descriptor DD is provided with an indication column DES where a data delimiter signal indicating whether reception data is terminated in the indicated buffer area or not is described. Since the number of buffer areas used for each frame is changed in accordance with the length of data of a variable length frame, the ineffective buffer area is reduced and only one descriptor is taken to immediately obtain the leading address of data of the next frame. Thus, the buffer memory use efficiency is improved and the data read time is shortened.

5. 发明专利

JPH01264302A OSCILLATION CIRCUIT 失效
公开(公告)号：JPH01264302A
公开(公告)日：1989-10-20
申请号：JP9147588
申请日：1988-04-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TOTANI TATSURO , NONAKA SOICHI , MATSUBARA KIYOSHI , BABA SHIRO
IPC分类号： H03B5/32
摘要： PURPOSE:To improve stability at the initial stage of oscillation using an oscillator by inserting a resistor between the input terminal of a gate circuit and that of an inverter in an oscillation circuit constituted in such a way that oscillation output can be obtained from the input terminal of the gate circuit via the inverter. CONSTITUTION:Basic constitution is provided in which a feedback resistor R is coupled between the input and the output terminals of a CMOS inverter 10, that is a circuit whose output changes corresponding to the change of input, The input terminal and the output terminal of the CMOS inverter 10 are coupled with an external/crystal terminal EXTAL and a crystal terminal XTAL via input protective resistors Ri1 and Ri2. A resistor Rd is provided between the input terminal of the CMOS inverter 10 and that of a CMOS inverter 11. An undesired incidental capacitance existing between the input terminal and the output terminal of the CMOS inverter 11 intends to suppress or offset input amplitude corresponding its output amplitude, however, the resistor Rd delays or limits the propagation of the capacitance. In such a way, it is possible to shorten a time required for the stabilization of the oscillation at the initial stage of self-oscillation with small input amplitude of the CMOS inverter 10 and unstable, and to heighten the stability at the initial stage of self-oscillation.

6. 发明专利

JPS6355637A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6355637A
公开(公告)日：1988-03-10
申请号：JP19886786
申请日：1986-08-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , KAWASAKI IKUYA , BABA SHIRO , HASEGAWA ATSUSHI , IWASAKI KAZUHIKO
IPC分类号： G06F9/30 , G06F9/34
摘要： PURPOSE:To omit an extended part to improve the code efficiency and to increase the instruction executing speed, by setting the short displacements received from a stack pointer and a frame pointer into an addressing mode. CONSTITUTION:A double operand instruction includes an operand designating part EA1 where the information needed for a 1st head word to calculate the effective address of a 1st operand is coded. The 1st word includes a class designating part CL, a mode designating part MD and a size designating part SZ1 in addition to the part EA1. An extended part EX1 for the 1st operand follows a 2nd word after the 1st word and an operation designating part OP is included in a n-th word following the part EX1.

7. 发明专利

JPS6353669A MICROPROCESSOR 失效
公开(公告)号：JPS6353669A
公开(公告)日：1988-03-07
申请号：JP19545586
申请日：1986-08-22
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TAKANO MAKOTO , HOSHI YASUHIKO , KURAKAZU KEIICHI , BABA SHIRO
IPC分类号： G06F13/28 , G06F13/42
摘要： PURPOSE:To simplify a system by transmitting a weight signal formed by a built-in program weight circuit to an external terminal in a microprocessor. CONSTITUTION:The program weight circuit (WAITC) supplies the weight signal to a CPU through an OR gate G and also transmits said signal to the other bus masters for supplying the weight signal through a driving circuit DV. A weight control signal WAIT outputted through the circuit DV is directly supplied to a memory access controller (DMAC). As the circuit DV realises wired logics in its output terminal, the weight signal supplied from the external terminal is supplied to the CPU through the OR gate G. And the WAITC receives the signal from the BUS and monitors that the DMAC doubles as a bus master. Therefore if there is a DMAC to become a bus master by using the WAITC, the system can be simplified.

8. 发明专利

DE69332551T2 未知
公开(公告)号：DE69332551T2
公开(公告)日：2003-08-14
申请号：DE69332551
申请日：1993-03-11
申请人： HITACHI LTD , HITACHI ULSI ENG CORP
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO MASANAO , TERASAWA MASAAKI , KURODA KENICHI , SHIBA KAZUYOSHI
IPC分类号： G06F12/06 , G06F9/445 , G06F12/00 , G06F15/78 , G11C7/10 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , G11C17/00 , H01L21/8247 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

9. 发明专利

DE69232232T2 未知
公开(公告)号：DE69232232T2
公开(公告)日：2002-08-29
申请号：DE69232232
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

10. 发明专利

DE69325533D1 未知
公开(公告)号：DE69325533D1
公开(公告)日：1999-08-12
申请号：DE69325533
申请日：1993-03-11
申请人： HITACHI LTD , HITACHI ULSI SYSTEMS CO
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO MASANAO , TERASAWA MASAAKI , KURODA KENICHI , SHIBA KAZUYOSHI
IPC分类号： G06F12/06 , G06F9/445 , G06F12/00 , G06F15/78 , G11C7/10 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , G11C17/00 , H01L21/8247 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

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