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1. 发明专利

JPS56152357A OFFSET POTENTIAL APPLYING METHOD 失效
公开(公告)号：JPS56152357A
公开(公告)日：1981-11-25
申请号：JP5508380
申请日：1980-04-25
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： FUHA MASAHIRO , YASUDA TOYOJI , TAKEI TADASHI , YOSHIDA SUMIO , OBARA SHINICHIROU
IPC分类号： H04B1/74 , H04B3/00 , H04B3/40 , H04L25/02
摘要： PURPOSE:To settle the output potential of the receiving circuit to a constant value, by connecting series resistances between both ends of the matching terminating resistance, which is connected between two lines of the balanced transmission line, and differential input terminals of the receiving circuit and by applying the offset potential across differential input terminals. CONSTITUTION:One end of matching terminating resistance 5 is connected to differential input terminal 6 of receiving circuit 8 through series resistance 10. The other end of resistance 5 is connected to differential input terminal 7 of circuit 8 through series resistance 11. At the normal operation time, the signal level from transmission circuit 1 and the noise level generated on balanced transmission line 4 are attenuated by resistances 10 and 11. For the release of transmission line 4, the short-circuit fault, or the fault or power break of circuit 1, the output potential at output terminal 9 of circuit 8 is settled to a constant potential because a constant offset potential is applied across terminals 6 and 7 of circuit 8.

2. 发明专利

JPS5444813A SIGNAL TRANSMISSION SYSTEM OF BALANCED BUS CIRCUIT 失效
公开(公告)号：JPS5444813A
公开(公告)日：1979-04-09
申请号：JP11143377
申请日：1977-09-16
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： MATSUNAGA HIROSHI , KANEKO YOSHIMASA , AOKI KUNIO , UNZAI MINORU , YOSHIDA SUMIO
IPC分类号： H04B3/54
摘要： PURPOSE:To attain stable bus transmission by canceling noise generated in couple of transmission lines, by setting the impedance of a high-voltage impedance much larger than that of a couple of transmission lines of the balancing type. CONSTITUTION:Output high-impedance voltage supply 25 is connected to any points of balanced bus transmission lines 21 and 22 to which a plural number of transmission circuits 23 and reception circuits 24 are connected. Impedance z of this voltage supply, when the characteristic impedance of the transmission line composed of transmission lines 21 and 22 is denoted by Z0, is fixed much greater than Z0, so that the balance of the transmission line can be kept for a transient time and driving time both by decreasing the potential level on transmission line 21 and 22 to the half of the driving amplitude of the transmission line. Consequently, noise generated on a couple of transmission lines 21 and 22 can be all canceled, so that stable bus transmission can be attained.

3. 发明专利

JPS5441643A M*N INSPECTION CIRCUIT SYSTEM 失效
公开(公告)号：JPS5441643A
公开(公告)日：1979-04-03
申请号：JP10793777
申请日：1977-09-09
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： AOKI TOSHIROU , YANAGISAWA TAKATOSHI , MIYAMOTO KOUICHI , YOSHIDA SUMIO , SEKI SHIYUUICHI
IPC分类号： G06F11/00 , G06F11/08 , H03M13/51
摘要： PURPOSE:To commonly use the system for the pass inspection for driving lines, by enabling to detect the output of each driving circuit with the current level.

4. 发明专利

JPS5413952A RELAY 失效
公开(公告)号：JPS5413952A
公开(公告)日：1979-02-01
申请号：JP8006977
申请日：1977-07-05
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： YANAGISAWA TAKATOSHI , SHIBUYA TADASHI , YOSHIDA SUMIO , MURAKAMI TOMOSHI , MIYAKE YASUSHI
IPC分类号： H01H51/28 , H01H50/44 , H01H63/00

5. 发明专利

JPS5469934A TERMINATION SYSTEM OF LOGIC CIRCUIT 失效
公开(公告)号：JPS5469934A
公开(公告)日：1979-06-05
申请号：JP13664277
申请日：1977-11-16
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： YOSHIDA SUMIO , KANEKO YOSHIMASA , AOKI KUNIO , UNZAI MINORU , OBARA SHINICHIROU
IPC分类号： H04L25/02 , H03K19/0175
摘要： PURPOSE:To reduce waveform distortion caused by a reflected signal by providing required terminating circuits to both the terminals of a transmission line to which a plural number of current change-over type digital integrated circuits (CML) are connected. CONSTITUTION:Terminating circuits composed of terminating resistances 13 and 15, and DC power supplies 14 and 16 are provided to terminals 11 and 12 of transmission line 1 to which CMLs 2 to 7 are connected, and resistance values of those terminating resistances 13 and 15 are set between 1.4 and 2.6Z0 denoting characteristic impedance of the line by Z0. As a result, reflection coefficients at terminals 11 and 12 are decreased to approximate one third, so that the waveform distortion will be reduced to one third of conventional one.

6. 发明专利

JPS5430715A SIGNAL TRANSMISSION SYSTEM OF BALANCED BUS CIRCUIT 失效
公开(公告)号：JPS5430715A
公开(公告)日：1979-03-07
申请号：JP9604877
申请日：1977-08-12
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： YOSHIDA SUMIO , KANEKO YOSHIMASA , AOKI KUNIO , UNZAI MINORU , MATSUNAGA HIROSHI
IPC分类号： H04B3/32 , H04L25/00 , H04L25/02
摘要： PURPOSE:To prevent noises from being generated by varying potential levels on both bus transmission lines in mutually-opposite directions, by interposing a voltage supply between a terminating circuit on the bus transmission line and the earth potential.

7. 发明专利

JPS522161A LOGIC CIRCUIT 失效
公开(公告)号：JPS522161A
公开(公告)日：1977-01-08
申请号：JP7657975
申请日：1975-06-24
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KUNIMI NOBUO , MUKAI HISAKAZU , TERADA YASUKAZU , HAYASAKA AKIO , YOSHIDA SUMIO
IPC分类号： H03K19/086
摘要： PURPOSE:To improve switching speed by connecting level shifting resistors of unit logic circuit in parallel.

8. 发明专利

JPS61212915A TWO-PHASE CLOCK GENERATING CIRCUIT 失效
公开(公告)号：JPS61212915A
公开(公告)日：1986-09-20
申请号：JP5228285
申请日：1985-03-18
申请人： HITACHI LTD
发明人： YOSHIDA SUMIO
IPC分类号： H03K3/027 , G06F1/04 , G06F1/06 , H03K3/037
摘要： PURPOSE:To facilitate troubleshooting of a fixed fault of a delay element by inserting a gate means interrupting a loop to each of two feedback loops. CONSTITUTION:A test signal of logical 1 is fed to test signal input terminals 11, 12 and a single phase clock signal is fed to the clock input terminal 1. An output of an NAND gate 3 is inputted to an NAND gate 4 via an AND gate 5 and a delay element 7 and the output of the NAND gate 4 is inputted to the NAND gate 3 via an AND gate 6 and the delay element 8 and they act like a 2-phase clock generating circuit. In conducting the circuit operation test, the test signal of logical 1 is fed alternately to the terminals 11, 12 to detect the logical value of the clock output terminals 13, 14.

9. 发明专利

JPS59172822A Noise filter 失效
标题翻译：噪声滤波器
公开(公告)号：JPS59172822A
公开(公告)日：1984-09-29
申请号：JP4712783
申请日：1983-03-23
申请人： Hitachi Ltd
发明人： YOSHIDA SUMIO
IPC分类号： H03H7/01 , H03H7/06 , H03H7/075
CPC分类号： H03H7/01
摘要： PURPOSE:To eliminate even a noise having a narrow pulse width and high energy density by using a coil and a capacitor to a circuit connecting a resistor and a coil in parallel. CONSTITUTION:The coil 3 and the capacitor 6 are connected respectively in series and parallel with the parallel circuit comprising the coil 4 and the resistor 5. In selecting values of each coil, the resistor and the capacitor so as to satisfy a prescribed relation, most of the current due to noise having a short pulse width flows to the resistor 5, is attenuated by the circuit constituted with the resistor 5 and the capacitor 6, and since almost no noise current flows to the coil 4, the attenuating oscillation is not produced. Since the amount of timewise change of the noise current flowing to the capacitor 6 is suppressed by the coil 3, the voltage drop caused by a residual inductance of a lead or the like of the capacitor 6 is decreased.
摘要翻译：目的：通过对连接电阻和线圈并联的电路使用线圈和电容器来消除甚至具有窄脉冲宽度和高能量密度的噪声。构成：线圈3和电容器6分别与包括线圈4和电阻器5的并联电路串联连接。在选择每个线圈，电阻器和电容器的值以满足规定的关系时，大多数由于具有短脉冲宽度的噪声导致的电流流向电阻器5，由电阻器5和电容器6构成的电路衰减，并且由于几乎没有噪声电流流向线圈4，所以不产生衰减振荡。由于线圈3抑制流向电容器6的噪声电流的时间变化量，所以由电容器6的引线等的残留电感引起的电压降降低。

10. 发明专利

JPS564937A REVERSIBLE COUNTER 失效
公开(公告)号：JPS564937A
公开(公告)日：1981-01-19
申请号：JP8019079
申请日：1979-06-27
申请人： HITACHI LTD
发明人： YOSHIDA SUMIO , SUGIYAMA KAORU
IPC分类号： H03K23/00 , H03K23/66
摘要： PURPOSE:To constitute a counter whose dividing ratio is expressed by one ''even number''-th with a small number of control elements by detecting the set state and fixed count-value state of a counter and then by exercising up-down control over the counter with a level signal based upon the detection result. CONSTITUTION:Reversible counter 2 counts clock pulses CP and its count direction is brought under the control of RSFF1. Fixed count value detecting circuits 3 and 4 detect the contents of counter 2 reaching a fixed count value and with their detection signals, FF1 is brought under set-reset control. In this case, pulse removing circuits 5 and 6 remove the error detection of circuits 3 and 4 due to difference in timing. Now, when counter 2 is to operate at dividing ratio 1/14, circuit 3 sets FF1 on detecting count value ''0'' and then counter 2 counts up; and circuit 4 resets FF1 on detecting count value ''7'' and counter 2 is brought under switching control to count down, counting up and down cyclically between ''0'' and ''7'', so that the counter will eventually operate at a division ratio of 1/14.

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