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1. 发明专利

JPH0736759A SEMICONDUCTOR FILING SYSTEM 失效
公开(公告)号：JPH0736759A
公开(公告)日：1995-02-07
申请号：JP17561993
申请日：1993-07-15
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI KEIYO ENG
发明人： KATAYAMA KUNIHIRO , KAKI KENICHI , OOKUBO CHIKAO , KIKUCHI TAKASHI , KISHI MASAMICHI , SUZUKI TAKESHI , KADOWAKI SHIGERU , TSUNEHIRO TAKASHI , TAKATANI YOSHIO , SAITO MANABU
IPC分类号： G06F12/00 , G06K19/07 , G11C16/02 , G11C16/06 , G11C17/00
摘要： PURPOSE:To provide a semiconductor filing system in which write speed on memory can be accelerated and a long service life, a low cost, and reliability can be attained. CONSTITUTION:This system is provided with a card controller 9 which controls the inside of a card and a microcomputer 7 which controls file data and the card controller 9. Furthermore, flash memory and a mask ROM(inexpensive) are used as memory 1 for file data storage as local memory 6, and the mask ROM is shared as memory 2 for attribute storage. Also, a PSRAM 13 is used as a control table 3 that is a part of data managing information(information to record the number of times of rewrite and to uniformalize the number of times of rewrite), a write buffer 4 for the acceleration of write speed, and a garbage buffer 5 when unrequired data erasure processing is performed.

2. 发明专利

JPH06243027A MEMORY CONTROLLER 失效
公开(公告)号：JPH06243027A
公开(公告)日：1994-09-02
申请号：JP2768793
申请日：1993-02-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKUCHI TAKASHI , OOKUBO CHIKAO
IPC分类号： G06F12/02
摘要： PURPOSE:To easily constitute a memory device which is most suitable for storing data of a desired bit length by using semiconductor memories different in bit constitution by changing a set point value or the like to an offset setting means. CONSTITUTION:When an external address (address 20000) is fetched into comparators CMP1-CMP9 in synchronism with the fall of an address strobe signal AS supplied from a CPU board, it is compared with addresses which are set in address registers ADR1-ADR9. The outputs CE1-CE5 of coincident comparators CM1-CM5 are changed to low levels. The memories MEM1-MEM4, of four pieces X eight constitution, are simultaneously accessed and the address to which an offset value is added is supplied to the memory MEM5. The addresses 20000, 120000, 220000 and 320000 are sequentially accessed. Thus, data of total 36 bits are outputted to a data bus 24.

3. 发明专利

JPH04151735A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04151735A
公开(公告)日：1992-05-25
申请号：JP27673290
申请日：1990-10-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OOKUBO CHIKAO , KIKUCHI TAKASHI , SAIE YASUHIKO , HATANO SUSUMU
IPC分类号： G06F9/44 , G06N7/02
摘要： PURPOSE:To enable a fuzzy inference by a few bus cycles by directly outputting the conclusive information of the fuzzy inference for the observational information being the object of the fuzzy inference, or outputting it after synthesizing it, based on the observational information and read information from a storage means. CONSTITUTION:This circuit is equipped with a condition memory 2 and a conclusion memory 3, as the storage means which store a conditional description and a conclusive description for constituting the production rule of the fuzzy inference. The conditional description and the conclusive description are stored in these storage means 2 and 3, and the bus cycle which performs access of them from the outside, and supplies the observational information, is activated, so that a logical operation and a temporary storing operation according to the rule of the fuzzy inference can be automatically operated according to an inside hardware. The conclusive information of the fuzzy inference for this observational information can be directly outputted, or the information obtained after synthesizing it can be outputted. Thus, the fuzzy inference can be realized by a digital method by a few bus cycle.

4. 发明专利

JPH03276489A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH03276489A
公开(公告)日：1991-12-06
申请号：JP7333590
申请日：1990-03-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OOKUBO CHIKAO , KIKUCHI TAKASHI
IPC分类号： G11C11/41
摘要： PURPOSE:To quickly retrieve data by discriminating the attribute of data taken in from the external and designating an access object area of a memory based on the discrimination result. CONSTITUTION:In the case of data write to a semiconductor storage device 9 where the data base of an artificial intelligence system is formed, data taken in from the external is held in a register 25 is transmitted to an AND circuit group 20 through a demultiplexer 24, and AND between input data and comparison bit segmenting information preliminarily set to a register 26 is operated to segment the comparison bits. The output of the AND circuit group 20 is transmitted to a comparator 14 to discriminate the attribute of input data, and the start address of a memory 22 is designated based on the discrimination result to designate the access object area of the memory 22. Thus, data reference of an attribute different from that of input data is omitted to increase the data retrieval speed.

5. 发明专利

JPH03141445A CACHE MEMORY DEVICE 失效
公开(公告)号：JPH03141445A
公开(公告)日：1991-06-17
申请号：JP27841389
申请日：1989-10-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUSE YASUFUMI , KIKUCHI TAKASHI , SAIE YASUHIKO , OOKUBO CHIKAO
IPC分类号： G06F12/12 , G06F12/08
摘要： PURPOSE:To improve the system throughput by fetching a data group belonging to an area having high access probability out of a main memory and initializing the data group. CONSTITUTION:A cache memory device 2 shares partly the storage information on a main memory 3 so as to attain a hierarchical structure of the memory 3. Then a data group CD belonging to an area having high access probability is fetched from the memory 3 and analyzed by a fetch control circuit 19. The circuit 19 also fetches the group CD as necessary regardless of a cache miss or cache hit state and sets the group CD. In such a constitution, the system throughput is improved.

6. 发明专利

JPS6226692A STATIC TYPE RAM 失效
公开(公告)号：JPS6226692A
公开(公告)日：1987-02-04
申请号：JP16417485
申请日：1985-07-26
申请人： HITACHI VLSI ENG , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TACHIMORI HIROSHI , FUKAZAWA TAKESHI , OOKUBO CHIKAO , FUKUDA HIROSHI , HATAKEYAMA AKIYOSHI
IPC分类号： G11C11/41 , G11C11/34
摘要： PURPOSE:To speed up an operation by providing an MOSFET for equalizing which is made to on state by the non-selective level of a selection signal supplied to a column switch MOSFET that connects a complementary data line to a common complementary data line. CONSTITUTION:When the complementary data lines of MOSFETs Q16, Q17 are made to the non-selective state by the supply of data line selection signals Y0, Y1 corresponding to the gates, Q16, Q17 are made to on state which corresponding column switches MOSFET Q12, Q13 and Q14, Q15 are made to off state, and equalizing is executed making complementary data lines D0, the inverse of D0 and D1, the inverse of D1 short-circuited state. Consequently, in the chip selection state to which address signals AX, AY are supplied, the level of complementary data lines D, the inverse of D connected to a memory cell according to actual selection timing of the memory cell, changes from level equal to each other according to memory information of the memory cell in case of reading operation, and changes according to writing signals in case of writing operation. Accordingly, the speeding up of the operation becomes possible.

7. 发明专利

JPH0877081A FILE MEMORY SYSTEM 失效
公开(公告)号：JPH0877081A
公开(公告)日：1996-03-22
申请号：JP23435994
申请日：1994-09-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOKOBE CHIHOKO , SAIE YASUHIKO , KIKUCHI TAKASHI , FUKUDA HIROSHI , SUZUKI TAKESHI , KADOWAKI SHIGERU , OOKUBO CHIKAO , KISHI MASAMICHI , KATAYAMA KUNIHIRO , KAKI KENICHI
IPC分类号： G06F12/16 , G06F12/00 , G11C16/02 , G11C16/06 , G11C17/00
摘要： PURPOSE: To provide the file memory system which prevents sector management data in a nonvolatile memory from being rewritten unnecessarily. CONSTITUTION: In the file memory system which stores data in a file, sector by sector, a nonvolatile storage device 5 which is electrically rewritable in block units has sector management data 51 showing use states by sectors. The sector management data are initially set in a volatile storage device 4 from the nonvolatile storage device 5 and a sector table 41 which has its contents updated according to file operation is formed. When the power supply to the volatile storage device 4 is stopped, the contents of the sector management data that the nonvolatile storage device 5 holds are compared in block units with the contents of the sector table 41 and only blocks where mismatching is detected are rewritten into the corresponding contents of the sector table 41.

8. 发明专利

JPH06259620A IC CARD 失效
公开(公告)号：JPH06259620A
公开(公告)日：1994-09-16
申请号：JP4622893
申请日：1993-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUKUDA HIROSHI , KIKUCHI TAKASHI , KATAYAMA KUNIHIRO , KAKI KENICHI , OOKUBO CHIKAO
IPC分类号： B42D15/10 , G06K19/077
摘要： PURPOSE:To provide the IC card of the SCSI type or an equivalent type conforming to a standard requiring a terminating resistance which is provided with a terminating resistance and is superior in heat radiation property. CONSTITUTION:A resistor group 6 consisting of 18 pairs of resistors R like films to be the terminating resistance is formed on a rear face 1a of a lower cover 1 of an IC card 100. A supply voltage feed line of wiring, an earth line, and respective signal lines of wiring in a resistance package part are electrically connected to a supply voltage feed line of wiring, an earth line, and respective corresponding signal lines on a printed board, on which an IC chip is mounted, through electric wires. Further, the IC card may be divided into a card main body incorporating an IC and a resistance card attachable to and detachable from it and the resistor group 6 may be formed on the rear face of the lower cover of the resistance card.

9. 发明专利

JPH04199340A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04199340A
公开(公告)日：1992-07-20
申请号：JP33161690
申请日：1990-11-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKUCHI TAKASHI , OOKUBO CHIKAO
IPC分类号： G06F12/00 , G06F12/06
摘要： PURPOSE:To improve the throughput of the system by providing two simultaneously accessible memory blocks and a buffer holding the data read out from one memory block in a semiconductor memory. CONSTITUTION:Two simultaneously accessible memory blocks MM1 and MM2 and a buffer BFF1 holding the data read out from one memory block are provided in the semiconductor memory to perform the data transfer between memory blocks MM1 and MM2 through this buffer BFF1. Therefore, as the data transfer such as garbage collection can be executed in one cycle in the memory as well as the external bus is not necessary to be used, the data transfer can be speeded up. Thus, the throughput of the system is improved.

10. 发明专利

JPH0482084A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0482084A
公开(公告)日：1992-03-16
申请号：JP19589190
申请日：1990-07-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FURUNOMA TOSHIHIKO , KIKUCHI TAKASHI , SAIKOU YASUHIKO , OOKUBO CHIKAO , FUSE YASUFUMI , NISHIMOTO KENJI , HATANO SUSUMU
IPC分类号： G11C11/401 , G11C11/407 , G11C11/409
摘要： PURPOSE:To perform the high-speed access of data spread over different word lines by providing an address control means performing an internal memory operation and an input/output control means reading or writing the data spread over different word lines to the outside en bloc. CONSTITUTION:The address control by an address counter 31 as an address control means in partial access and the read or write of the data spread over the different word lines by the data input/output control with bi-directional buffer circuits 36 to 39 as a data input/output control means are performed at one bus cycle. In short, the address is updated by the address counter 31, and bi-directional buffer circuits 36 to 39 read the data spread over the different word lines to the outside en bloc, and the data input/output control to be written spread over different word lines is performed. Thus, the high-speed access of the data spread over different word lines can be performed.

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