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1. 发明专利

JPS6459949A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6459949A
公开(公告)日：1989-03-07
申请号：JP21709187
申请日：1987-08-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UCHIDA KEN , MEGURO SATOSHI , NAGASAWA KOICHI , ISHII SEIICHI , IWAI TOSHIJI , KAMIGAKI YOSHIAKI , UCHIBORI KIYOBUMI , FURUSAWA KAZUNORI , TERASAWA MASAAKI , MATSUBARA KIYOSHI
IPC分类号： H01L21/8247 , H01L21/822 , H01L27/04 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792 , H01L29/861
摘要： PURPOSE:To improve a diode which functions as a voltage limiter in reliability by a method wherein ions are implanted into the PN junction section of the diode so as to develop the defect in it. CONSTITUTION:A mask is formed, which is composed of a connecting hole 21B of a diode D2 provided to a region A that is annealed at high temperature of 900 deg.C-1000 deg.C and a resist film of a pattern where a part of a memory cell M1 that the information of a mask ROM is to be written in is opened. Next, P-type impurity, for instance, boron is introduced for the formation of a damaged region 24 in a region A and a P-type semiconductor region 14 in a channel region of the memory cell M1 in a region C. Then, wirings 22A, 22B, and 22C, a data line DL, and other aluminum wirings are successively formed. A mask of a resist film is removed after patterning is performed. Thereafter, H2 annealing is performed at temperature of 450 deg.C, more or less. The annealing performed at about 450 deg.C after the formation of the aluminum wirings 22A, 22B, 22C, and the data line DL does not cure the defect, which is developed in the damaged region 24 formed on the diode D2, so that the diode D2 can be improved in property.

2. 发明专利

JPS628559A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS628559A
公开(公告)日：1987-01-16
申请号：JP14655085
申请日：1985-07-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UCHIBORI KIYOBUMI , NAKAMURA HIDEAKI
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To prevent software errors and to improve electric reliability with respect to keeping of data, by providing a semiconductor region, to which a fixed potential is applied, in the vicinity of a data storing part, in a semiconductor integrated circuit device provided with a memory function. CONSTITUTION:A memory cell is formed by transfer MISFETs Qs1 and Qs2, which are to become switching elements, and a flip-flop circuit having a pair of input/output terminals, which is to become a data storing part. a semiconductor region 3 is embedded in a well region 2 at a position in the vicinity of the data storing part of the memory cell. The region 3 is extended in the direction of a row (or in the direction of a column). A power source voltage Vcc is applied to the semiconductor region 3, and a semiconductor region L at a fixed potential is formed. Thus part of minority carriers yielded by alpha rays is absorbed into the semiconductor region 3. Therefore, software errors are prevented, and electric reliability in keeping information data can be improved.

3. 发明专利

JPH07211804A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07211804A
公开(公告)日：1995-08-11
申请号：JP29416994
申请日：1994-11-29
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To increase the level of integration of an SRAM by forming an insulating film above the gate electrode of an MISFET for driving, and forming a second conductivity type polycrystalline silicon film which is electrically connected with the drain region of the MISFET for driving and used as the gate electrode of an MISFET for load, above the insulating film. CONSTITUTION:An gate insulating film 5 is formed on the main surface of a P-type well region. An N type semiconductor region 11 which is used as an N type semiconductor region 8, a source region and a drain region is formed on the main surface part of a well region with which a gate electrode 7 is connected through an N-type semiconductor region 9 used as a part of a source region and a part of a drain region and a connection hole 6. A layer insulating film 12 is formed on the whole part of the substrate containing the upper part of the gate electrode 7, and a gate insulating film 15 is formed on the whole surface of the substrate, so as to cover a gate electrode 14. The channel forming regions 17A, the drain regions 17B, and the source regions 17C of MISFET's Qp1, Qp2 for loads are formed in order above the gate insulating film 15.

4. 发明专利

JPH056669A MOS TYPE RAM 失效
公开(公告)号：JPH056669A
公开(公告)日：1993-01-14
申请号：JP29414991
申请日：1991-11-11
申请人： HITACHI LTD
发明人： UCHIBORI KIYOBUMI
IPC分类号： G11C11/41 , G11C11/409 , G11C11/417
摘要： PURPOSE:To prevent a through current of a data input buffer at the time of reading data by controlling an operation of the buffer by a combination of a chip selection signal and a write/read control signal. CONSTITUTION:When a chip select signal CS becomes a low level so that a reading operation is conducted, a write enable signal WE does not alter from a high level but remain thereat. Thus, a control signal DIC remains at a high level and does not change. Accordingly, in the meantime until read data from a data output buffer DOB is output, an input/output terminal I/O becomes an intermediate level at a high impedance. Thus, even if MOSFETs Q1, Q3 are simultaneously turned on, a MOSFET Q2 is turned off and hence a large through current does not flow thereby to prevent an erroneous operation.

5. 发明专利

JPH01191395A OUTPUT CIRCUIT 失效
公开(公告)号：JPH01191395A
公开(公告)日：1989-08-01
申请号：JP1250288
申请日：1988-01-25
申请人： HITACHI LTD
发明人： UCHIBORI KIYOBUMI , MORIWAKI NOBUYUKI
IPC分类号： G11C11/417 , G11C11/34 , G11C11/409 , H01L27/10
摘要： PURPOSE:To speed up an output circuit without increasing a consuming current by disposing a data inverting means for inverting an outputted data signal in the prestep of a final output step and temporarily supplying reverse data obtained by inverting the previous data immediately before an output signal is changed to the output step. CONSTITUTION:Based on the output data signals DT, -DT supplied from an internal circuit, AND gates G1, G2 forming the driving signal of MOSFET Q1, Q2 and exclusive OR logical gates G3, G4 are disposed on the prestep of the output step to temporarily supply the reverse data obtained by inverting the previous data to the output step immediately before the output signals DT, -DT are changed. Namely, according to the reverse data supplied to the output step, output transistors Q1, Q2 are reversely operated to a preceding time to preset an output terminal to Vcc/2. Thereby, an equalizing MOSFET is not required nor passes a through current to speed up the output circuit without increasing the consuming current.

6. 发明专利

JPS62241358A ONE-TIME PROGRAM TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62241358A
公开(公告)日：1987-10-22
申请号：JP8411786
申请日：1986-04-14
申请人： HITACHI LTD
发明人： UCHIBORI KIYOBUMI , KOMARU TAKESHI , MUTO TADASHI , KOJIMA KAZUO
IPC分类号： H01L23/29 , G11C16/18 , H01L21/8247 , H01L23/31 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To erase resins, and to improve reliability by potting an ultraviolet-ray transmitting type resin and further potting an ultraviolet-ray non-transmitting type resin onto the ultraviolet-ray transmitting type resin when an EPROM element is molded with the resins. CONSTITUTION:An EPROM element 5 is die-bonded at a predetermined position on a conductor layer 2, and electrodes 6 on the element 5 and the conductor layer 2 are connected by wires 7 for connectors through a wire bonding system. The electrodes 6 and the conductor layer 2 are wire-bonded, a potting frame 8 consisting of the quality of a material such as glass epoxy is fitted to a glass epoxy film substrate 1 by epoxy adhesives and the like in order to stop a flow on resin potting, and an ultraviolet-ray transmitting type resin 9 is potted first, and cured, thus molding the EPROM element 5. An overall byte writing test is conducted at the stage, and the possibility of writing is checked. The assembly of the element is aged by being positioned at a high temperature, and the capacity of data-hold is checked. The capacity of data-hold is checked, and data are erased by ultraviolet irradiation.

7. 发明专利

JPS58100300A CMOS MEMORY 失效
公开(公告)号：JPS58100300A
公开(公告)日：1983-06-14
申请号：JP19858981
申请日：1981-12-11
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： UCHIBORI KIYOBUMI , AKIMA ISAO
IPC分类号： G11C11/413 , G06F1/00 , G06F1/26 , G06F12/16 , G11C11/34 , H02J9/00
摘要： PURPOSE:To simplify the design by installing a power supply voltage detecting circuit and a logical operation circuit in an IC and to float each input pin by a power supply voltage drop signal. CONSTITUTION:A logical operation circuit section 3 and a power supply voltage detecting circuit section 4 are constituted by CMOSs and they are incorporated in an IC, and, at the same time, in addition to a chip select CS, other pins, for example, pins of address ADR, data input Din, write-enable WE, etc., are made reactive by using the output of the power supply voltage detecting circuit section 4.

8. 发明专利

JPS5848960A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5848960A
公开(公告)日：1983-03-23
申请号：JP15272982
申请日：1982-09-03
申请人： HITACHI LTD
发明人： MASUHARA TOSHIAKI , MINATO OSAMU , SASAKI TOSHIO , SAKAI YOSHIO , UCHIBORI KIYOBUMI , YASUI NORIMASA
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To prevent latch-up by forming a P type well biassed to ground potential to a semiconductor surface between a circuit connected to an input or output terminal and an internal circuit in a C-MOS.IC in which a PMOS transistor is shaped to an N type substrate and an NMOS transistor into the P type well formed into the substrate. CONSTITUTION:A polycrystal Si gate 17, a P drain region 16 and a P type source region 15 are formed to the N type Si substrate 5 and used as the PMOS transistor, a polycrystal Si gate 19, an N type drain region 18 and an N type source region 20 are shaped into the P type well 6 molded to the substrate 5 and employed as the NMOS transistor, and the C-MOS internal circuit is formed by these transistors. Likewise, an Si gate 11, an N type drain 10 and a source 12 are shaped into the P type well 7 and used as the NMOS transistor, a P type base extracting region 13 and an N type emitter region 14 are formed into the P type well 8, and a bipolar output circuit is formed. These wells 7, 6 are zero-biassed by P type regions 9, 21 shaped to the wells 7, 6.

9. 发明专利

JPS5671948A IC CHIP 失效
公开(公告)号：JPS5671948A
公开(公告)日：1981-06-15
申请号：JP14889579
申请日：1979-11-19
申请人： HITACHI LTD
发明人： HONDA MINORU , NAGAI AKIRA , UCHIBORI KIYOBUMI
IPC分类号： H01L21/66
摘要： PURPOSE:To ensure accurate size measuring by keeping upon the check of electric characteristic one or two dummy bump electrodes provided in addition to bump electrodes for the check faultless when the electrodes are shaped semispherical or into a table form on an IC chip using solder. CONSTITUTION:A plurality of semispherical or table-shaped solder bump electrodes 2 are provided on the both sides of an IC chip body 1 to check electric characteristic. Besides, one dummy solder bump electrode 3 or two dummy solder bump electrodes 4 are provided which are not used for check. The electrode 2 is used to check electrode characteristic but the electrodes 3 or 4 are left not used for check. Thereby, even if the electrode is deformed upon the contact of a probe, the electrodes 3 or 4 are kept faultless so that size measuring can be made accurately.

10. 发明专利

JPS5651836A PELLET INSPECTING APPARATUS 失效
公开(公告)号：JPS5651836A
公开(公告)日：1981-05-09
申请号：JP12683679
申请日：1979-10-03
申请人： HITACHI LTD , HITACHI OME ELECTRONIC CO
发明人： UCHIBORI KIYOBUMI , SASAKI MASAAKI , YAMAMOTO AKIRA , YASUI NORIMASA , NISHIMURA KOUTAROU , WAKIMOTO HARUMI , NOSAKA TOSHIO
IPC分类号： H01L21/66
摘要： PURPOSE:To permit the existence of a pin-hole or foreign matter on and the surface geometry of a pellet to be automatically inspected by scanning the pellet surface with a narrow light beam and observing the variation of the reflection intensity of the light beam. CONSTITUTION:From a light source 3, a narrow light beam 5 is drawn through a collimator 4 or the like, and the whole desired surfaces of a pellet 2 are successively scanned with the beam 5 by a vibrating mirror 6 or the like. The reflected light 7 of the beam 5 is received by a light receiver 8 to observe the variation of the reflected light intensity, and a pellet 2 having a reflectance above or below a given intensity range is selected. This permits a pin-hole or foreign matter having an extremely minute diameter to be inspected as well as the inspection speed to be much higher than the eye inspection. Moreover, the inspection can be made automatic.

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