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1. 发明专利

JP2003197763A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003197763A
公开(公告)日：2003-07-11
申请号：JP2001391270
申请日：2001-12-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , RENESAS E JP SEMICONDUCTOR INC
发明人： YOSHIDA SEIJI , SHIBA KAZUYOSHI , TANIGUCHI YASUHIRO , YAMAKOSHI HIDEAKI , YAMABE KAZUHARU , TAKADA HIDENORI , TOYOKAWA SHIGEYA , MATSUSHITA TOMOHIKO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a high electrostatic discharge withstanding voltage and high reliability in electrostatic discharge protection by optimizing the constitution of an electrostatic discharge protecting MOSFET. SOLUTION: The semiconductor integrated circuit has an electrostatic discharge protecting MOSFET. Its gate and source are directly coupled and its drain is connected to an external terminal to make electrostatic charge applied to the external terminal flow between the drain and the source, thereby attenuating the amount of charge to be sent to following circuits. The electrostatic discharge protecting MOSFET is formed so that a minimum drain withstanding voltage between the source and the drain expressed with a function of the gate voltage is less than those of MOSFETs used in the following circuits, e.g. lower than a power voltage. COPYRIGHT: (C)2003,JPO

2. 发明专利

JP2002305255A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002305255A
公开(公告)日：2002-10-18
申请号：JP2001108390
申请日：2001-04-06
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YAMABE KAZUHARU , YOSHIDA SEIJI , TOYOKAWA SHIGEYA , MATSUOKA MASAMICHI , HASHIMOTO KOJI
IPC分类号： H01L27/092 , H01L21/8238
摘要： PROBLEM TO BE SOLVED: To efficiently provide a method by which pMOS transistors having two kinds of threshold voltages can be manufactured. SOLUTION: After polycrystalline silicon films are deposited on n-type well regions 6 and 7 and p-type well regions 8 and 9 isolated from the regions 6 and 7 by element isolation regions 4 and 5, p- and n-type impurities are respectively injected into the polycrystalline silicon films in a region 6a and regions 8a and 9a through ion implantation. Then the pMOS transistors having different threshold voltages are formed in the regions 6a and 7a, by forming p-type diffusion regions 11b on the main surface of a semiconductor substrate 1 by diffusing the p-type impurity injected into the polycrystalline film in the region 6a to the substrate 1 side through heat treatment. In addition, nMOS transistors are respectively formed in the regions 8a and 9a.

3. 发明专利

JP2000196017A SEMICONDUCTOR DEVICE AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JP2000196017A
公开(公告)日：2000-07-14
申请号：JP36968698
申请日：1998-12-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HASHIMOTO KOJI , KURODA KENICHI , IKEDA SHUJI , YOSHIDA SEIJI , TOYOKAWA SHIGEYA
IPC分类号： H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To maintain high performance of the MISFET of a logic circuit, and to reduce the leakage currents of the selected MISFET of a DRAM memory cell. SOLUTION: A gap-insulating film and a gate electrode 17 are formed on the main face of a semiconductor substrate 1, and a sidewall 21 is formed on substrate sidewall, and the semiconductor substrate 1 is oxidized in a state such that a cap-insulating film is present on the gate electrode 17 and a silicon oxide film 22 can be formed. Afterwards, the cap-insulating film is selectively removed, and the silicon oxide film 22 in second and third regions B and C is etched by using a photoresist film, and the silicon oxide film 22 is allowed to be left only on a source/drain in a first area A. A silicide technique is used in this state so that a silicide film 29 can be formed on the gate electrode 17 in the first, second, and third regions A, B, and C, and on the source/drain in the second and third regions B and C.

4. 发明专利

JP2003142602A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003142602A
公开(公告)日：2003-05-16
申请号：JP2001337249
申请日：2001-11-02
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUOKA MASAMICHI , HASHIMOTO KOJI , YOSHIDA SEIJI , TOYOKAWA SHIGEYA , YAMABE KAZUHARU
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce the number of photomasks used to manufacture a DRAM and to improve the manufacturing yield of the DRAM. SOLUTION: The method for manufacturing the semiconductor integrated circuit device comprises the steps of dry etching a silicon oxide film 46 (and a silicon nitride film 45 of its lower layer and a silicon oxide film 40) of a logic region, prior to the step of forming an upper electrode 56 of a capacity element C on a memory region; and forming through holes 52, 53. The method further comprises the steps of depositing the upper electrode material (W film 55, TiN films 54, 50) in a groove 47 and on the film 46, then removing the upper electrode material of the exterior of the groove 47 by a chemimechanical polishing method, thereby forming the electrode 56 in the groove 47, and thereafter simultaneously forming Al alloy wirings connected to the electrode 56 and Al alloy wirings connected to the plug 57 in the through holes 52, 53 on the silicon oxide film 46.

5. 发明专利

JP2001250860A METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001250860A
公开(公告)日：2001-09-14
申请号：JP2000058357
申请日：2000-03-03
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TOYOKAWA SHIGEYA , YOSHIDA SEIJI , MATSUOKA MASAMICHI , HASHIMOTO KOJI , KURODA KENICHI
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor integrated circuit device for improving the variation margin of CMP, reducing a recess, and improving MOS characteristics. SOLUTION: In the manufacturing method of a semiconductor device using an element separation groove where an insulating film is buried into a groove formed on a substrate 1 for separating elements, a film used as a mask in a process for forming a groove for separating elements and a film used as a stopper film in a process for refilling silicon oxide film into the groove are made of a silicon nitride film 3 and a silicon oxide film 4, respectively, as a lamination structure film L.

6. 发明专利

JP2001308297A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001308297A
公开(公告)日：2001-11-02
申请号：JP2000126357
申请日：2000-04-26
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TOYOKAWA SHIGEYA , YOSHIDA SEIJI , MATSUOKA MASAMICHI , HASHIMOTO KOJI , KURODA KENICHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide technology capable of adopting an ESD element in a semiconductor integrated circuit device mounting DRAM and logic LSI. SOLUTION: The high voltage resistant CMOS structure ESD element is constituted by an n-channel type MISFETQn providing a plurality of strip-like high resistant areas 9 comprising only a low impurity concentration n-type semiconductor area 4 on a part of a drain, and p-channel type MISFETQp providing the plurality of the strip-like high resistant areas 9 comprising only a low impurity concentration ptype semiconductor area 11 on a part of a source.

7. 发明专利

JP2001057411A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2001057411A
公开(公告)日：2001-02-27
申请号：JP23103199
申请日：1999-08-18
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TOYOKAWA SHIGEYA , HASHIMOTO KOJI , KURODA KENICHI , YOSHIDA SEIJI , IWAKI TOSHIYUKI , MATSUOKA MASAMICHI
IPC分类号： H01L27/10 , H01L21/02 , H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce contact resistance by preventing reduction of a contact area between a plug and a barrier layer in a DRAM in which a bit line is formed on the plug composed of a polycrystalline silicon film via the barrier layer. SOLUTION: When a plug 21 composed of a polycrystalline silicon film is formed inside a contact hole 19 to which a bit line BL is connected, the upper surface of the plug 21 is recessed to a level lower than the upper end portion of the contact hole 19. A plug 22 composed of a laminated layer film of a TiN film 26 and a W film 27 is formed on the plug 21. Subsequently, a bit line BL having a thinner width than the diameter of the contact hole 19 is formed by patterning the W film deposited on the contact hole 19. At this time, the W film 27 constituting the plug 22 is also etched in the contact hole 19, but the TiN film 26 constituting the other part of the plug 22 is hardly etched.

8. 发明专利

JPH0637325A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0637325A
公开(公告)日：1994-02-10
申请号：JP18785792
申请日：1992-07-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TOYOKAWA SHIGEYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To reduce a difference in level between the end part of a charge storage gate electrode and a field insulation film by a method wherein a first gate material is embedded between field insulation films and flattening is made so that the position of the end part of the material is leveled substantially with the position of the surface of the field insulation film. CONSTITUTION:A first gate material 6A is formed on the whole surface of a substrate including a first gate insulation film 5 and a field insulation film 4 and a mask 7 is formed thereon. Then, etching is executed and thereby the first gate material 6A is put in a state of being embedded between the field insulation films 4. The position of the surface of the end part in the gate-width direction of the first gate material 6A filled in is made equal to the position of the surface of the field insulation film 4, in the direction vertical to the surface of an active region of a P well region 2. The end part in the gate-width direction of the first gate material 6A is formed in a self-alignment manner in relation to the field insulation film 4, and thus flattening can be made so that the position of the surface of the end part in the gate-width direction of the first gate material 6A is leveled substantially with the position of the surface of the field insulation film 4.

9. 发明专利

JPH06267977A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06267977A
公开(公告)日：1994-09-22
申请号：JP5167493
申请日：1993-03-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ARIGA SEIICHI , MATSUDA NOZOMI , YOSHIDA SEIJI , MORI CHIEMI , TOYOKAWA SHIGEYA , IWANAGA TAIJI , KUNIMOTO YUKINORI
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/784
摘要： PURPOSE:To improve an electric characteristic of a MISFET by reducing resistance of a diffusion layer directly under a contact hole and a contact resistance between this diffusion layer and a conductive layer. CONSTITUTION:Prior to a process of forming a contact hole by opening an insulating film 3 between the gates 2, 2 of a pair of a MISFET formed on a semiconductor substrate 1, ion implantation is performed on the semiconductor substrate 1 in the contact hole forming region from the direction to be slanting being seen from a section of a semiconductor substrate 1 along the extending direction of the gate electrode 2 and to be vertical being seen from the section of the semiconductor substrate 1 along the direction orthogonal to the extending direction of the gate electrode 2. Next, after the contact hole is formed, a conductive layer is formed on the upper part of the MISFET in order to electrically connect the conductive layer to a diffusion layer 4 directly under the contact hole through the contact hole.

10. 发明专利

JPH06252169A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING THEREOF 失效
公开(公告)号：JPH06252169A
公开(公告)日：1994-09-09
申请号：JP3186193
申请日：1993-02-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA SEIJI , TOYOKAWA SHIGEYA , MATSUDA NOZOMI , ARIGA SEIICHI , MORI CHIEMI , IWANAGA TAIJI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/784
摘要： PURPOSE:To make it possible to form a channel region, a source region, and a drain region with self-alignment without using a host mask by depositing a semiconductor layer on a gate electrode and on a main surface through an insulation film and etching back the semiconductor layer until the gate insulation film is exposed. CONSTITUTION:In a semiconductor device of a lower section gate structure where a gate electrode 13 is formed on the insulating main surface 12, the gate electrode 13 is formed on the insulating main surface 12 of a substrate 11, and the gate electrode 13 is covered with a gate insulation film 14 to form first semiconductor layer 15 on the upper gate electrode 13 and on the upper section of the main surface 12 through the insulation film 14. Further, the first semiconductor layer 15 on the gate insulation film 14 positioned on the upper section of the gate electrode 13 is removed to form a source region 15a and a drain 15b are formed on both ends of the gate electrode 13. Furthermore, a second semiconductor layer 16 to serve as an opposite conductivity type channel region with respect to the first semiconductor layer 15 is formed on the insulation film 14 on the upper section of the gate electrode 14 and on the first semiconductor layer 15.

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