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1. 发明专利

JPH113599A SEMICONDUCTOR MEMORY AND DATA PROCESSING DEVICE 失效
公开(公告)号：JPH113599A
公开(公告)日：1999-01-06
申请号：JP15469697
申请日：1997-06-12
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS , HITACHI TOBU SEMICONDUCTOR LTD
发明人： SEKIGUCHI KAZUO , MATSUMOTO KENJI , KAWAJIRI YOSHIKI , HASEGAWA NAOHIRO , NAKANO YASUSHI
IPC分类号： G11C17/00 , G11C17/12
摘要： PROBLEM TO BE SOLVED: To improve yield by enlarging operation margin. SOLUTION: Two reference lines R1, R2 are provided and switches 73, 74 for switching synchronously the reference lines R1, R2 to bit line selection. View of line capacity of bit lines is made equal to view of line capacity of reference lines in the case of watching from a differential stage side by switching of the reference lines, enlarging operation margin is attained by reducing influence of line capacity.

2. 发明专利

JPH076600A METHOD AND DEVICE FOR INSPECTING ELECTRIC CHARACTERISTIC OF SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH076600A
公开(公告)日：1995-01-10
申请号：JP17373493
申请日：1993-06-21
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： TAKAGI SUSUMU , NAKANO YASUSHI , TOMITA KEIJI , MAYUZUMI HIDEAKI
IPC分类号： G11C29/00 , G11C29/06 , H01L21/66
摘要： PURPOSE:To provide a device capable of simultaneously testing many pieces of storage and monitoring them in full-time. CONSTITUTION:Data write are executed for many pieces of semiconductor storage 2 so that respective read output signals of mutually respective output terminals become a common level. Thereafter, the write data of respective semiconductor storages are read out, and respective output signals are sent to an input terminal 44 of a defective information extraction circuit 40 respectively where an AND circuit 42 and an OR circuit 43 are connected in parallel each other. By comparing the output signal level of the AND circuit with the output signal level of the OR circuit in the defective information extraction circuit 40, the defect of the data write operation is extracted. Thus, since the defects of the data write operation in many pieces of semiconductor storages are detected simyltaneously, testing time and an increase cost are suppressed. Since the defects of the data write operation of the whole semiconductor storages are monitored in full-time, the overlooking of a temporary defect, etc., is evaded.

3. 发明专利

JPH1153877A SUBSTRATE TYPE ELECTRONIC CIRCUIT AND PRE-PAID CARD 失效
公开(公告)号：JPH1153877A
公开(公告)日：1999-02-26
申请号：JP20911097
申请日：1997-08-04
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： MIYATA AYUMI , YAMADA YUICHIRO , OCHIAI TOSHIHIKO , NAKANO YASUSHI
IPC分类号： G07F7/08 , G06K17/00 , G06K19/07 , G06K19/10 , G11C5/00
摘要： PROBLEM TO BE SOLVED: To provide, in a low cost, a pre-paid card and the other IC card having higher security. SOLUTION: This circuit comprises, within a card, a memory 11 which does no allow reprogramming such as, for example, a mask ROM, a memory 12 which is electrically reprogrammable but is not electrically erased such as EPROM and is comparatively simplified semiconductor logical circuit chip 13 which outputs data only when the predetermined conditions are satisfied in comparison with the data in the memory. The reprogrammable first memory 11 is caused to store the initial data at the time of issuance such as the available limit value, while the second memory 12 is caused to store the amount data or metering data after the use and when the data in the second memory 12 is larger than the data in the first memory 11, data is never output or a card is recognized as an illegal card.

4. 发明专利

JPH06338200A METHOD AND DEVICE FOR INSPECTING ELECTRICAL CHARACTERISTIC OF SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH06338200A
公开(公告)日：1994-12-06
申请号：JP14550293
申请日：1993-05-25
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： TAKAGI SUSUMU , NAKANO YASUSHI , TOMITA KEIJI , MAYUZUMI HIDEAKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C29/00 , G11C29/56 , H01L21/66
摘要： PURPOSE:To simultaneously test numerous pieces of EEPROMs by inhibiting writing operations against cells to be inspected for which it has been verified that data writing has been executed normally. CONSTITUTION:An ALPG 23 simultaneously executes data writing verifying inspections on the cells of a plurality of EEPROM devices 2. A comparator 24 compares an expected value signal from the ALPG 23 with the output signal from one cell to be inspected and discriminates that the cell is normal when both signals are coincident or defective when both signals are not coincident. A retry counter 25 counts the current number of retrying times based on the discriminated result of the comparator 24 and compares the count value with the compared value. A chip enable(CE) control circuit 27, the output terminal of which is simultaneously connected to the cells of the EEPROM 2 and input terminal of which is connected to the output terminal of the comparator 24, inhibits writing to the cells for which it has been verified that data writing has been executed normally at the retrying time.

5. 发明专利

JPH0757499A TEST METHOD FOR ELECTRICAL CHARACTERISTIC OF SEMICONDUCTOR MEMORY AND DEVICE THEREFOR 失效
公开(公告)号：JPH0757499A
公开(公告)日：1995-03-03
申请号：JP21515193
申请日：1993-08-06
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： TAKAGI SUSUMU , NAKANO YASUSHI , TOMITA KEIJI
IPC分类号： G11C29/00 , G11C29/56 , H01L21/66
摘要： PURPOSE:To avoid that a test time is affected by dispersion of responsiveness of a device and to shorten a test time for verifying writing data by discriminating whether writing data is performed within an allowable time or not in plural semiconductor memories. CONSTITUTION:When aging is performed in a EEPROM, many EEPROMs 2 being an object of aging are mounted in freely attachably and detachably, these are connected in parallel each other. After these groups connected to a testing section, a power supply is turned on by a command of a CPU, and a clock signal and a reset signal are made in an 'H' level. After that, an address is cleared and counted by a retry counter 27, successively, a writing command is set by an ALPG 24 and data are simultaneously written by a driving section 21, a verify command is set, and the command is performed. Next, a response signals are inputted to each time comparator 23 any time, an allowable time from an allowable time register 22 is compared with response signals from each ROM, and it is discriminated whether this time is within an allowable time or not.

6. 发明专利

DE69325496T2 未知
公开(公告)号：DE69325496T2
公开(公告)日：2000-02-24
申请号：DE69325496
申请日：1993-12-01
申请人： HITACHI LTD , JAPAN BROADCASTING CORP
发明人： YAMAGISHI TOSHIO , NANBA MASAKAZU , EGAMI NORIFUMI , TANIOKA KENKICHI , KURASHIGE MITSUHIRO , TSUJI KAZUTAKA , KANEKO YOSHIYUKI , MIKISHIMA TATSUO , NAGATSUMA KAZUYUKI , OHSHIMA TETSUYA , NAKANO YASUSHI
IPC分类号： H01J29/04 , H01J29/45 , H01J31/26 , H01J31/38 , H04N5/225 , H04N5/335 , H04N5/355 , H04N5/357 , H04N5/369 , H04N5/378
摘要： A photoconductive target having a transparent electrode (102) and a photoconductive layer (103) on a transparent substrate (101) is disposed opposite to a plurality of integrated electron emitters having electron emitters (106) and gate electrodes (104). A plurality of electron emitters applying electron beams to the photoconductive target are temporally changed over by an electron emitter selector circuit (107) and a gate selector circuit (108). Thereby, signal charge generated and stored in the photoconductive layer is read. A time-series electric signal corresponding to a spatial distribution of the incident light is generated. A thin imaging apparatus suitable for a larger area is thus provided.

7. 发明专利

DE69325496D1 未知
公开(公告)号：DE69325496D1
公开(公告)日：1999-08-05
申请号：DE69325496
申请日：1993-12-01
申请人： HITACHI LTD , JAPAN BROADCASTING CORP
发明人： YAMAGISHI TOSHIO , NANBA MASAKAZU , EGAMI NORIFUMI , TANIOKA KENKICHI , KURASHIGE MITSUHIRO , TSUJI KAZUTAKA , KANEKO YOSHIYUKI , MIKISHIMA TATSUO , NAGATSUMA KAZUUYUKI , OHSHIMA TETSUYA , NAKANO YASUSHI
IPC分类号： H01J29/04 , H01J29/45 , H01J31/26 , H01J31/38 , H04N5/225 , H04N5/335 , H04N5/355 , H04N5/357 , H04N5/369 , H04N5/378
摘要： A photoconductive target having a transparent electrode (102) and a photoconductive layer (103) on a transparent substrate (101) is disposed opposite to a plurality of integrated electron emitters having electron emitters (106) and gate electrodes (104). A plurality of electron emitters applying electron beams to the photoconductive target are temporally changed over by an electron emitter selector circuit (107) and a gate selector circuit (108). Thereby, signal charge generated and stored in the photoconductive layer is read. A time-series electric signal corresponding to a spatial distribution of the incident light is generated. A thin imaging apparatus suitable for a larger area is thus provided.

8. 发明专利

JP2001188213A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JP2001188213A
公开(公告)日：2001-07-10
申请号：JP37416899
申请日：1999-12-28
申请人： HITACHI LTD
发明人： NAKANO YASUSHI , ORITSUKI RYOJI
IPC分类号： G01R31/00 , G02F1/13 , G02F1/1345
摘要： PROBLEM TO BE SOLVED: To inspect disconnection of signal wiring of a thin film transistor in a manufacturing process of a high definition display liquid crystal panel of which the display area is split into two upper and lower parts. SOLUTION: In a thin film transistor substrate forming a liquid crystal panel of which the display area is split into two parts of a top display area AR-U and a bottom display area AR-D to be driven at the same time, the presence or absence of disconnection is inspected by whether or not currents are flowing through top and bottom drain lines, by connecting an inspection purpose thin film transistor, at the time of inspecting disconnection, across a top side drain line DL-U and a bottom side drain line DL-D split in the center part of the top and bottom display areas, applying such voltages to a common gate line CGL of the inspection purpose thin film transistor CTFT and across the top side drain line DL-U and the bottom side drain line DL-D as to operate the inspection purpose thin film transistor CTFT, and thereby bringing the top drain lines DL-U and the bottom drain line into conduction with each other.

9. 发明专利

JPH11221532A SUBSTRATE WASHING METHOD AND SUBSTRATE WASHING DEVICE 失效
公开(公告)号：JPH11221532A
公开(公告)日：1999-08-17
申请号：JP2410398
申请日：1998-02-05
申请人： HITACHI LTD
发明人： NAKANO YASUSHI , KANEKO TOSHITERU , NISHIMURA YUICHI , UCHIDA MORIO
IPC分类号： B08B3/08 , C11D7/04 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To drastically decrease the amt. of the static electricity to be generated and to prevent the occurrence of a defect occurring in static electricity, as metallic wiring dissolution, by using the washing water prepd. by dissolving a salt not contg. metal elements or gaseous carbon dioxide at a high concn. into ultrapure water to lower the resistivity thereof. SOLUTION: This washing device senses the flow rate of the ultrapure water flowing into a washing water pipe 110a by a flow meter 111. Ammonium carbonate water which is the salt not contg. the metal elements in a tank 113 is intermittently injected by an injection pump 114 in accordance with the flow rate into a washing water pipe 110a. At this time, if the flow rate of the ultrapure water sensed by the flow meter 111 is large, the intermittent intervals are made shorter by the control of a controller 115 and if the flow rate is small, the intermittent intervals are made longer to a maintain the concn. of the ammonium carbonate which is the washing water constant. The setting of the concn. is executed by inputting desired electroconductivity into the controller 115. The information from an electroconductivity meter 112 is fed back to the injection pump 114 to maintain the desired electroconductivity of the washing water. For example, a static mixer 117 is disposed between the injection pump 114 and the electroconductivity meter 112 to well mix the ultrapure water and the ammonium carbonate water.

10. 发明专利

JPH09329796A LIQUID CRYSTAL DISPLAY SUBSTRATE 失效
公开(公告)号：JPH09329796A
公开(公告)日：1997-12-22
申请号：JP14691296
申请日：1996-06-10
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： HIROSHIMA MINORU , ISODA TAKASHI , NAKANO YASUSHI , SUZUKI MASAHIKO , OUGIICHI KIMITOSHI
IPC分类号： G02F1/13 , G02F1/1345
摘要： PROBLEM TO BE SOLVED: To protect a chip-on-glass type active matrix substrate from static electricity and to inspect electric defects on the substrate by arranging each non-linear resistor element between the connection terminal of each gate line or each drain line and an input terminal to a driving IC. SOLUTION: Non-linear resistor elements NL arranged between connection terminals GP, DP and input terminals IDP, IGP and capable of discharging static electricity entered into gate lines G or drain lines D to the direction of a guard ring GR are connected in common by one short-circuit line SLN in each of driving ICs (ICG, ICD) and the line SLN is connected to the guard ring GR on the outside of a cutting line CT. Thereby static electricity entered into the gate lines G or the drain lines D is diffused and absorbed to the guard ring GR through the common short-circuit line SLN prepared in each driving IC, voltage between the gate lines G and the drain lines D is eased and breakdown or the like due to static electricity can be prevented.

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