专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH1027905A SEMICONDUCTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1027905A
公开(公告)日：1998-01-27
申请号：JP18321696
申请日：1996-07-12
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , HITACHI TOBU SEMICONDUCTOR LTD
发明人： NAKAZAWA YOSHITO , KOBAYASHI MASAYOSHI , FUJITA YUZURU , TAMURA YASUO , KANAZAWA TAKAMITSU , NUMAZAWA SUMUTO , IIJIMA TETSUO , YANOKURA EIJI
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a vertical metal insulator field effect transistor(MISFET) Q which can lower an on-resistance which ensuring a withstand voltage of the device. SOLUTION: In the semiconductor device having a vertical metal insulator field effect transistor(MISFET) Q, a P type epitaxial layer 1B is used as a drain region, an N type semiconductor region 6 formed on a major surface of the epitaxial layer 1B is used as a channel formation region, and a P type semiconductor region formed on a major surface of the N type semiconductor region 6 is used as a source region. In this case, an impurity concentration distribution of a region 2A having a thickness corresponding to a height from a bottom face of the epitaxial layer 1B to a bottom face of the region 6 is deigned to have such a concentration gradient that the impurity concentration gradually decreases from the bottom face of the epitaxial layer 1B toward the major surface thereof.

2. 发明专利

JPH07240522A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07240522A
公开(公告)日：1995-09-12
申请号：JP3227894
申请日：1994-03-02
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICOM SYST KK
发明人： NAKURA KENICHI , HARUYAMA MASAMITSU , FUJITA YUZURU , TAMURA YASUO , MARUYAMA YASUO
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
摘要： PURPOSE:To provide a technique for easily manufacturing a semiconductor integrated circuit device excellent in high-frequency characteristics and power gain characteristics. CONSTITUTION:A P-type semiconductor region 8 higher in impurity concentration than a P-type semiconductor region 2 where a MOSFET is formed is provided under N-type semiconductor regions 9 and 12 which constitute the source region of the MOSFET, whereby a resistor connected to a capacity CGS between a gate electrode 5 and the N-type semiconductor region 12 is enlarged in current path, so that the region 12 is lessened in resistance, and consequently a high-performance MOSFET high in power gain can be obtained through a simple manufacturing technique as kept high in electrical properties.

3. 发明专利

JPS62287659A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62287659A
公开(公告)日：1987-12-14
申请号：JP13015786
申请日：1986-06-06
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KURODA KENICHI , KOMORI KAZUHIRO , TAMURA YASUO , NAGASHIMA HIDEAKI , HARADA KENICHI
IPC分类号： H02H7/20 , H01L27/02 , H01L27/06 , H01L29/78 , H03F1/00
摘要： PURPOSE:To improve a static breakdown preventing circuit in its capability of withstanding static voltages and to enlarge an input signal margin by a method wherein a device is constituted of a clamping n-channel MISFET and a p-channel MISFET installed between said clamping n-channel MISFET and an external terminal. CONSTITUTION:A static breakdown preventing circuit I is constituted of a MISFET Qnc and MISFET Qp1 provided in a stage prior to the MISFET Qnc. A positive surge voltage is moderated by the MISFET Qp1 whose voltage- withstanding capability in an avalanche state is higher than that of the MISFET Qnc, and the thus-moderated positive surge voltage is inputted into the MISFET Qnc. lt follows therefore that the MISFET Qnc is protected from static breakdown and the static breakdown preventing circuit II is improved in its capability of handling higher static voltages. In addition, with the static breakdown preventing circuit II being capable of accepting a positive signal equivalent to the reverse-direction breakdown voltage present in a semiconductor region 6 that is the drain region of the MISFET Qnc, a larger input signal margin may be established.

4. 发明专利

JPH0480966A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0480966A
公开(公告)日：1992-03-13
申请号：JP19577890
申请日：1990-07-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAMURA YASUO
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To prevent a MISFET where an LDD structure is adopted from deteriorating in electrical properties by a method wherein a point where impurity concentration becomes maximal is set in a first semiconductor region at a depth substantially identical to the junction depth a second semiconductor region or below, and a third semiconductor region whose conductivity type is identical to those of the first and the second semiconductor region and which is higher than the second semiconductor region in impurity concentration is provided between the first semiconductor region and wiring. CONSTITUTION:A point where impurity concentration becomes maximal is set in an N-type semiconductor region 8 of a MISFET where an LDD structure is adopted at a depth substantially identical to the junction depth of an N-type semiconductor region 6 or below. A carrier transfer path in the N-type semiconductor region 8 near to a channel forming region side is provided deep in the depthwise direction of the N-type semiconductor region 8, whereby the electrical field effect of a gate electrode on the transfer path can be lessened, so that hot carriers which are induced near the N-type semiconductor region 8 and trapped in a gate insulating film 3 can be lessened, a threshold voltage is lessened in fluctuation, and thus a MISFET where an LDD structure is adopted can be improved in electrical properties.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式