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1. 发明专利

JPH07240522A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07240522A
公开(公告)日：1995-09-12
申请号：JP3227894
申请日：1994-03-02
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICOM SYST KK
发明人： NAKURA KENICHI , HARUYAMA MASAMITSU , FUJITA YUZURU , TAMURA YASUO , MARUYAMA YASUO
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
摘要： PURPOSE:To provide a technique for easily manufacturing a semiconductor integrated circuit device excellent in high-frequency characteristics and power gain characteristics. CONSTITUTION:A P-type semiconductor region 8 higher in impurity concentration than a P-type semiconductor region 2 where a MOSFET is formed is provided under N-type semiconductor regions 9 and 12 which constitute the source region of the MOSFET, whereby a resistor connected to a capacity CGS between a gate electrode 5 and the N-type semiconductor region 12 is enlarged in current path, so that the region 12 is lessened in resistance, and consequently a high-performance MOSFET high in power gain can be obtained through a simple manufacturing technique as kept high in electrical properties.

2. 发明专利

JPH10335642A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10335642A
公开(公告)日：1998-12-18
申请号：JP14742597
申请日：1997-06-05
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICROCOMPUTER SYST
发明人： MARUYAMA YASUO , NAKURA KENICHI , SATO TAKAHIRO , NAGANO HIROMI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent increase of source wiring resistance which is caused by increase of length of stripes, by forming conductor layers which brings an electrode conductor layer in continuity with a source leading-out wiring connected with a source region, on a semiconductor substrate in the respective stripe parts. SOLUTION: A source leading-out wiring 10 connected with the source region 8 of an MISFET has a continuity with a substrate conductor layer 1, in a linkage part, through a connecting layer 12 formed in a semiconductor substrate. The substrate conductor layer 1 has a continuity with a source electrode 13 formed on the back of the substrate conductor layer 1 as a facing surface of the semiconductor substrate main surface, and an electrode conductor layer is constituted of the source electrode 13 and the substrate conductor layer 1. The source leading-out wiring 10 and the substrate conductor layer 1 are connected, in the respective stripe parts, through conductor layers 14 formed on the semiconductor substrate between the respective cells of the respective stripe parts divided into a plurality of cells. Thereby increase of source wiring resistance which is to be caused by increase of length of the stripes can be prevented.

3. 发明专利

JPH09181300A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH09181300A
公开(公告)日：1997-07-11
申请号：JP33516395
申请日：1995-12-22
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICROCOMPUTER SYST
发明人： MARUYAMA YASUO , YOSHIDA ISAO , SATO TAKAHIRO , NAGANO HIROMI
IPC分类号： H01L29/10 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a power MOSFET for amplifying high-frequency power in which the breakdown voltage of a drain does not drop even when the MOSFET is operated at a low power supply voltage. SOLUTION: Since a p-type semiconductor area 20 which has the same conductivity as that of a semiconductor substrate 1 (epitaxial layer 1B) and contains an impurity at a high concentration is formed immediately below a contact area 7 comprising part of the drain area of a power MOSFET (Q), the junction breakdown of the drain is prevented by generating an avalanche yield between the semiconductor area 20 and the substrate 1(epitaxial layer 1B) before the electric field intensity in an offset area 6 at the end section of a gate electrode 4 reaches a breakdown value.

4. 发明专利

JPH05243565A 失效
公开(公告)号：JPH05243565A
公开(公告)日：1993-09-21
申请号：JP4272092
申请日：1992-02-28
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： MARUYAMA YASUO , HARUYAMA MASAMITSU , OOTAKA SHIGEO , OKABE TAKEAKI
IPC分类号： H01L21/768 , H01L29/78 , H01L29/784 , H01L21/90
摘要： PURPOSE:To enhance the operation characteristics and the degree of integration of a semiconductor device by forming a gate electrode and a mask layer, by forming with these as masks a semiconductor region of a low impurity concentration and a reversely conductive type to the mask, by forming an interlayer film, and by forming a semiconductor region of a high impurity concentration and the reversely conductive type in the region where the interlayer film on the mask layer and other mask layer have been removed. CONSTITUTION:A gate electrode 7 is formed on the main surface of a semiconductor substrate 1 through a gate insulation film 4, and a mask layer is formed with the material as the same as that of the gate electrode 7 at the position separated from the gate electrode 7 in the direction of gate length on the region forming a semiconductor region of a high concentration. Next, a semiconductor region 11 with a low impurity concentration having a conductive type reversely to the semiconductor substrate 1 is formed on the main surface portion of the semiconductor substrate 1 with the gate electrode 7 and a mask layer respectively as masks, and then an interlayer film 15 is formed on the upper layer of the gate electrode 7 and the mask layer. Next, the interlayer film 15 on the mask layer is removed, the mask layer is removed, and a semiconductor region 22 with a high impurity concentration having a conductive type reversely to the semiconductor substrate 1 is formed on the main surface portion of the semiconductor substrate 1 of the removed region.

5. 发明专利

JP2003068674A Semiconductor device and production method therefor 审中-公开
标题翻译：半导体器件及其生产方法
公开(公告)号：JP2003068674A
公开(公告)日：2003-03-07
申请号：JP2001260721
申请日：2001-08-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUJII YUJI , SATO AKIHIKO , IHAYAZAKA TAKASHI , MARUYAMA YASUO , HATORI KAZUO
IPC分类号： H01L21/28
摘要： PROBLEM TO BE SOLVED: To reduce the process for gold foil spread (SPB) as a post-process in a production method for semiconductor device, a process for inspecting the presence/absence of an oxide film, and to provide a process for removing oxides, when the oxide is attached.
SOLUTION: In the semiconductor device, having an electrode on the surface (rear side) of a semiconductor wafer facing a circuit element forming surface (front side), the rear electrode is a multilayer electrode, with which an NiSi alloy layer, Ti or V layer, Ni layer, AuGe alloy layer and Au layer are successively laminated from the rear side of the semiconductor wafer.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了减少用于半导体器件的制造方法中的金箔扩散（SPB）作为后处理的工艺，检查氧化膜的存在/不存在的方法，以及提供除去氧化物的工艺当附着氧化物时。解决方案：在半导体器件中，在面向电路元件形成表面（正面）的半导体晶片的表面（后侧）上具有电极，后电极是多层电极，NiSi合金层Ti或V 层，Ni层，AuGe合金层和Au层从半导体晶片的后侧依次层叠。

6. 发明专利

JPS62183133A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62183133A
公开(公告)日：1987-08-11
申请号：JP2374086
申请日：1986-02-07
申请人： HITACHI LTD
发明人： MARUYAMA YASUO , SUDA MINORU
IPC分类号： H01L21/60
摘要： PURPOSE:To improve the hermetic property as well as the reliability of a semiconductor device, by bonding semiconductor conducting terminals of silicon or the like previously provided with an aluminum layer to external connection terminals so that bonding wires are bonded to the aluminum layers, and heating and melting low-melting frit glass for sealing a ceramic package so that the ceramic package hermetically contains the elements thus wire-bonded. CONSTITUTION:An aluminum layer 19 is formed on the top face of each of silicon chips 16 and 17. The silicon chips 16 and 17 are then bonded to an end of external connection terminals 14 and 15, respectively, by means of AuSi eutectic 18. A semiconductor chip 22 is bonded at a predetermined position on an external connection terminal 21 by means of the AuSi eutectic 18. They are wire bonded with bonding wires of aluminum 24. Subsequently, low-melting frit glass 13 is heated and molten. Even if the chips are exposed to a temperature of about 400-450 deg.C during this heating process, no purple plague occurs since there is no Au at the bonding positions of the bonding wires 24.

7. 发明专利

JPH08181308A INSULATED GATE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08181308A
公开(公告)日：1996-07-12
申请号：JP32601094
申请日：1994-12-27
申请人： HITACHI LTD
发明人： YOSHIDA ISAO , KATSUEDA MINEO , MARUYAMA YASUO
IPC分类号： H01L29/78 , H01L29/423 , H01L29/45 , H01L29/49
摘要： PURPOSE: To obtain an insulated gate semiconductor device in which resistance to every gate from a gate bonding part is reduced, in which an unbalance between respective gate resistances is eliminated so as to improve a high-frequency characteristic and which is not limited by the current capacity of a first-layer metal layer so as to make an output high. CONSTITUTION: A two-layer structure is formed in such a way that first-layer aluminum layers are connected in parallel on polycrystal silicon gate electrodes 9. The gates which are adjacent are connected outside a channel region while the two-layer structure is kept. Central parts of the respective adjacent gates are connected by a second-layer extruded aluminum electrode 17 via opening parts 40. A gate bonding part 41 is formed in the center of the extruded electrode 17. A source electrode and a drain electrode are formed as a two-layer structure by first-layer aluminum layers 10, 11 and second-layer aluminum layers 15, 16.

8. 发明专利

JPH0886671A SEMICONDUCTOR SENSOR 失效
公开(公告)号：JPH0886671A
公开(公告)日：1996-04-02
申请号：JP22295394
申请日：1994-09-19
申请人： HITACHI LTD
发明人： SHIMADA SATOSHI , UKAI SEIICHI , TAKAHASHI YUKIO , SASE AKIRA , SHIMAZOE MICHITAKA , MARUYAMA YASUO , HIDA TOMOYUKI
IPC分类号： G01F1/68 , B81B1/00 , G01D3/028 , G01D21/00 , G01F1/692 , G01F15/04 , G01L9/00 , G01L9/04 , G01L9/06 , G01N27/00 , H01L29/84
摘要： PURPOSE: To eliminate the thermal hysteresis by connecting a substrate with a high or highest potential of power supply, extending the thin shield film for a group of detection element over the thick part of the substrate and connecting the thin shield film with the substrate potential through a connection film thereby connecting the shield film surely with a wiring and setting the shield film potential at a predetermined level. CONSTITUTION: Thickness of a thin shield film 6 is set thinner than an insulation layer 9 formed at a thin part 12 and the thin shield film 6 is kept at a constant potential by contriving the structure at a connection film part 7. Inclination angle of the connection end face at the connection film part 7 is set at 70 deg. or less so that two creeping faces at the connection film part 7 are covered. After formation of the thin shield film 6, a thick connection film part 7 is formed out of a different material. Thickness of the shield film 6 is set at 0.1μm or less.

9. 发明专利

JPH07321315A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07321315A
公开(公告)日：1995-12-08
申请号：JP11262994
申请日：1994-05-26
申请人： HITACHI LTD
发明人： MARUYAMA YASUO , YANOKURA EIJI , SEKI TATSUHIRO , FUJITA YUZURU
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To reduce the ON resistance of a lateral MISFET by increasing the breakdown voltage of a drain region at a first semiconductor region and compensating the reduction in an impurity concentration at the surface region of the first semiconductor region at a second semiconductor region. CONSTITUTION:An offset region 7 of a lateral MISFETQ is formed by an n-type semiconductor region 5 which is formed on the main surface of a semiconductor substrate 1 and where the peak value of an impurity concentration distribution is set to a position which is deeper than the main surface from the main surface of the semiconductor substrate 1 toward the depth direction and an n-type semiconductor region 6 which is formed on the main surface of the n-type semiconductor region 5 and where the peak value of the impurity concentration distribution is set to a position which is shallower than the peak value of the impurity concentration distribution of the n-type semiconductor region 5, thus increasing the breakdown voltage of a drain region and reducing the resistance of an offset region 7 and hence reducing the UN resistance of a lateral MISFETQ and increasing the power gain of the title semiconductor device.

10. 发明专利

JPS60200546A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60200546A
公开(公告)日：1985-10-11
申请号：JP5602584
申请日：1984-03-26
申请人： HITACHI LTD
发明人： MARUYAMA YASUO , HAGIWARA YOSHIMI
IPC分类号： H01L23/12 , H01L21/52 , H01L21/58 , H01L23/28 , H01L23/492
摘要： PURPOSE:To improve the withstand voltage of a semiconductor device of the structure coated with a chip by forming a groove along a chip securing region on the main surface of a supporting plate. CONSTITUTION:A groove 15 formed along the edge of a securing region of a chip 3 is formed on the main surface of a header 1. The groove 15 coincides at the inner peripheral edge with the edge of a securing region of the chip 3. The depth of the groove 15 may be in the same degree as or shallower than the width of the groove. The sectional size of the groove 15 is decided in coincidence with the amount of resin flowed and coated on the chip. Since a chip securing region surrounded by the groove 15 coincides with the size of the chip, the chip 3 automatically moves so that the center of the chip 3 coincides with the center of the chip securing area due to the surface tension of melted solder 2, is secured in the state, and enhanced in the securing accuracy of the chip. Therefore, the positioning work for the chip in the following assembling steps is facilitated, and the productivity in the manufacture of the transistor can be improved.

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