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1. 发明专利

JPH09160831A INFORMATION PROCESSOR 失效
公开(公告)号：JPH09160831A
公开(公告)日：1997-06-20
申请号：JP31998995
申请日：1995-12-08
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NISHIMOTO JUNICHI , YOSHIOKA SHINICHI , TAMAKI SANEAKI , MATSUI SHIGESUMI , TAKAKUBO KATSUJI , HASHIMOTO KOJI , TATEZAWA TAKESHI , FURUYAMA MIKIO
IPC分类号： G06F12/14 , G06F21/24
摘要： PROBLEM TO BE SOLVED: To protect the contents of a memory which is specially desired not to be read, e.g. a ROM or RAM, by providing an instruction level setting circuit and an execution level judging circuit which judges whether or not data are allowed to be read out or written according to the level of the level setting circuit. SOLUTION: An access level setting circuit decodes addresses and transfers levels by the addresses to a CPU through a bus 103. An access level judging circuit judges whether or not data is accessed by using a command sent from the CPU through a bus 101 and compares the level of the data access itself sent through a bus 014 with the level of an instruction itself issuing data access sent through a bus 105 when it is judged that the data is accessed. When this judging circuit allows the access, the driving of buses 107 and 108 connecting the CPU, and a memory and a peripheral circuit is controlled through a bus 106.

2. 发明专利

DE69529374T2 未知
公开(公告)号：DE69529374T2
公开(公告)日：2003-10-23
申请号：DE69529374
申请日：1995-09-11
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

3. 发明专利

DE69529374D1 未知
公开(公告)号：DE69529374D1
公开(公告)日：2003-02-20
申请号：DE69529374
申请日：1995-09-11
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

4. 发明专利

DE69520718T2 未知
公开(公告)号：DE69520718T2
公开(公告)日：2001-08-02
申请号：DE69520718
申请日：1995-09-01
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

5. 发明专利

DE69520718D1 未知
公开(公告)号：DE69520718D1
公开(公告)日：2001-05-23
申请号：DE69520718
申请日：1995-09-01
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

6. 发明专利

JP2003109399A SEMICONDUCTOR MEMORY AND DESIGN AND DEVELOPMENT METHOD FOR SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：JP2003109399A
公开(公告)日：2003-04-11
申请号：JP2001299658
申请日：2001-09-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KOIKE TAKESHI , TAMAKI SANEAKI , MAEDA NORIAKI , NORISUE KATSUHIRO , UEDA YUKIO
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To shorten a design and development period in the case of that a plurality kinds of semiconductor memory of which constitution of memory mats are different are developed or a semiconductor integrated circuit incorporating such a memory is developed. SOLUTION: In the case a plurality of memory mats of which column constitution are mutually different are designed, constitution of column selecting circuits can be varied in accordance with constitution of memory mats. Concretely, a column selecting circuit is constituted so that a memory cell connected to an odd numbered word line and a memory cell connected to an even numbered word line are opposite direction mutually, in an order of selection of a plurality of columns belonging to the same bit column, memory cell belonging to an odd numbered bit and a memory cell belonging to an even numbered bit are opposite direction mutually, in an order of selection of a plurality of columns belonging to the same bit column, in an order of selection of a plurality of columns of each bit.

7. 发明专利

JPH08320829A DATA PROCESSOR 失效
公开(公告)号：JPH08320829A
公开(公告)日：1996-12-03
申请号：JP24087395
申请日：1995-08-25
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , NARITA SUSUMU , TAMAKI SANEAKI , KAWASAKI IKUYA
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： PURPOSE: To access an address conversion buffer by an MOV instruction and perform operation for invalidating an entry, etc., by comparing retrieved address information that an entry of a specified area has with the information that write data has. CONSTITUTION: For write access to a cache memory CACHE-M or address conversion buffer TLB, address information for specifying an object to be written is stored in a register R1 according to a specific address format. Then the data transfer MOV instruction is executed and then while the data in a register R0 is regarded as a transfer source, the data are written at the address position of the cache memory CACHE-M or address conversion buffer TLB specified by the register R1. Supporting associative writing guarantees the operation for invalidating an entry without fail since the retrieved address information which is not considered only by address specification are regarded as a condition of whether or not writing is enabled.

8. 发明专利

JP2001306396A CACHE MEMORY 失效
公开(公告)号：JP2001306396A
公开(公告)日：2001-11-02
申请号：JP2000115585
申请日：2000-04-17
申请人： HITACHI LTD
发明人： TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10
摘要： PROBLEM TO BE SOLVED: To provide a cache memory capable of furthermore reducing power consumption by furthermore reducing hit decision and data reading processing capable of omitting a cache memory. SOLUTION: Adjacent entry information indicating whether continuous data having the same tag address an entry address are stored in one or plural entry addresses continued to the front or back of a certain entry address or not is stored in a storage area correspondingly to each entry address of a data array. When the existence of data to be continuously accessed in the data array is confirmed on the basis of the adjacent entry information at the time of executing memory accesses to reference addresses to be successively and continuously changed, a CPU is allowed to access the data array without comparing the data of the tag address.

9. 发明专利

JPH08320830A DATA PROCESSOR 失效
公开(公告)号：JPH08320830A
公开(公告)日：1996-12-03
申请号：JP24087195
申请日：1995-08-25
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , TAMAKI SANEAKI , NARITA SUSUMU
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： PURPOSE: To support plural page sizes without increasing chip occupation area or power consumption by allowing respective storage areas, where information on correspondence between logical page numbers and physical page numbers is stored, to be accessed with common index addresses. CONSTITUTION: A logical address space is divided into units called logical pages, and logical addresses are converted into physical addresses, page by page. A buffer memory 1 like an address conversion buffer is used in common to plural logical pages which are variable in size. A set associative cache memory which is equipped with a storage area for storing the correspondence information including a logical page number VPN and a physical page number PPN corresponding to it and has plural banks 11-14 accessed with the common index addresses 2 is used as the buffer memory 1.

10. 发明专利

JPH11184752A DATA PROCESSOR AND SYSTEM THEREFOR 失效
公开(公告)号：JPH11184752A
公开(公告)日：1999-07-09
申请号：JP35033097
申请日：1997-12-19
申请人： HITACHI LTD
发明人： TAMAKI SANEAKI , SHIMOYAMA NAOHIKO
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To maintain the equivalent data reading speed as a cash memory in the form of the parallel operation of an address array and a data array, and to realize low power consumption. SOLUTION: A CPU 101 outputs a fist signal 104 indicating whether or not this time access is a continuous access address to the previous access address. A cache memory 4 is provided with a flag means which is turned into a first state when a cache line to be selected by an index operation in the next access should be the same as that in this time access when it is indicated that the first signal is the continuous access address in the next access by the CPU, and which is turned into a second state otherwise. When it is indicated that the first signal is the continuous access address at the time of access by the CPU, and the flag means is turned into the first state, the memory operation of an address array 109 is suppressed, and only a data array 110 is operated.

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