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1. 发明专利

JPH1117019A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING WIRING PROGRAMMING ELEMENT USED FOR THE DEVICE 失效
公开(公告)号：JPH1117019A
公开(公告)日：1999-01-22
申请号：JP18063397
申请日：1997-06-20
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： SEKIGUCHI TOMONORI , KIMURA SHINICHIRO , TANAKA HITOSHI , NODA HIROMASA , AOKI MASAKAZU , KAWAMOTO HIROSHI
IPC分类号： H01L21/82 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/112
摘要： PROBLEM TO BE SOLVED: To make it possible to form an element in microscopic size by a method wherein a wiring programming element, to be selectively cut, is composed of the top wiring layer, and after formation of the surface of the first insulating film, the second insulating film, covering the cutting surface and the aperture part of the programming wiring part, is formed. SOLUTION: The top layer of a metal wiring layer M3, which constitutes a wiring programming element to be selectively cut corresponding to the result of the electric test on an electronic circuit, is formed on an interlayer insulating film INS4. Then, the surface of the first insulating film INS5, excluding the fixed wiring of the electronic circuit provided on the interlayer insulating film IND4 is formed. A program cutting part HP and the surface of a pad part, is formed. Subsequently, resist is applied on the first insulating film INS5, and an aperture is provided on the resist on the upper part of the wiring programming element to be cut by EB(electron beam) lithography. Lastyl, the first insulating film INS5 is etched using the resist as a mask, and the second insulating film INS6 is deposited.

2. 发明专利

DE3483709D1 未知
公开(公告)号：DE3483709D1
公开(公告)日：1991-01-17
申请号：DE3483709
申请日：1984-09-28
申请人： HITACHI LTD
发明人： SUNAMI HIDEO , OHKURA MAKOTO , MIYAO MASANOBU , KUSUKAWA KIKUO , MONIWA MASAHIRO , KIMURA SHINICHIRO , WARABISAKO TERUNORI , KURE TOKUO
IPC分类号： H01L21/762 , H01L27/108 , H01L27/10
摘要： A semiconductor memory uses the side wall part of a recess (17) dug in a Si substrate (10, 25) as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a capacitor (8, 18, 19, 25) having a large capacitance can be attained without increasing the breakdown of an insulator film (18, 19) ascribable to the thinning of the insulator film. In addition, a vertical switching transistor (4, 12, 15, 21) is formed on the Si substrate (10, 25), whereby the Si substrate can be entirely utilized for the formation of the capacitor.

3. 发明专利

DE3484313D1 未知
公开(公告)号：DE3484313D1
公开(公告)日：1991-04-25
申请号：DE3484313
申请日：1984-12-14
申请人： HITACHI LTD
发明人： SUNAMI HIDEO , OHKURA MAKOTO , KIMURA SHINICHIRO
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PCT No. PCT/JP84/00597 Sec. 371 Date Aug. 14, 1985 Sec. 102(e) Date Aug. 14, 1985 PCT Filed Dec. 14, 1984 PCT Pub. No. WO85/02716 PCT Pub. Date Jun. 20, 1985.A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.

4. 发明专利

DE3368351D1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 未知
公开(公告)号：DE3368351D1
公开(公告)日：1987-01-22
申请号：DE3368351
申请日：1983-06-22
申请人： HITACHI LTD
发明人： MIYAO MASANOBU , OHKURA MAKOTO , TAKEMOTO IWAO , WARABISAKO TERUNORI , MUKAI KIICHIRO , HARUTA RYO , KIMURA SHINICHIRO , TOKUYAMA TAKASHI
IPC分类号： H01L27/00 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/786
摘要： At least one layer of insulator film (61-63) and single-crystal film (71-73) are alternately stacked and deposited on a surface of a semiconductor substrate (50), and an impurity-doped region (104-113) formed in each semiconductor film (71-73) is used as a gate, source or drain of a MOS transistor.Thus, a three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the semiconductor substrate surface, but also in a direction perpendicular thereto.

5. 发明公开

EP0166003A4 SEMICONDUCTOR INTEGRATED CIRCUIT. 失效
标题翻译：半导体集成电路。
公开(公告)号：EP0166003A4
公开(公告)日：1987-06-29
申请号：EP85900191
申请日：1984-12-14
申请人： HITACHI LTD
发明人： SUNAMI HIDEO , OHKURA MAKOTO , KIMURA SHINICHIRO
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7827 , H01L21/8221 , H01L21/823885 , H01L27/0688 , H01L27/092 , H01L27/1104 , H01L29/78642

6. 发明专利

JP2010251366A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010251366A
公开(公告)日：2010-11-04
申请号：JP2009096015
申请日：2009-04-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUGII NOBUYUKI , TSUCHIYA RYUTA , KIMURA SHINICHIRO , ISHIGAKI TAKASHI , MORITA YUSUKE , YOSHIMOTO HIROYUKI
IPC分类号： H01L29/786 , H01L21/76 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283
摘要： PROBLEM TO BE SOLVED: To provide a technique for achieving low power consumption of a semiconductor device by improving a shape at a boundary between an SOI layer of an SOI substrate and shallow-trench element isolation.
SOLUTION: A position (SOI edge 10) at which a main surface of a silicon substrate 3 and a line extending along a side surface of an SOI layer 1 intersect with each other is retreated in a direction opposite to shallow-trench element isolation 4 compared to a position (STI edge 9) at which a line extending along a sidewall 8 of a shallow trench and a line extending along the main surface of the silicon substrate 3 intersect with each other. A corner of the silicon substrate 3 at the STI edge 9 has a curved surface.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过改善SOI衬底的SOI层和浅沟槽元件隔离之间的边界处的形状来实现半导体器件的低功耗的技术。解决方案：硅衬底3的主表面和沿着SOI层1的侧表面延伸的线彼此相交的位置（SOI边缘10）在与浅沟槽元件相反的方向上退避隔离4与沿着浅沟槽的侧壁8延伸的线和沿着硅衬底3的主表面延伸的线相交的位置（STI边缘9）相比。硅衬底3在STI边缘9处的角部具有弯曲表面。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2008205006A Semiconductor light-emitting element, optoelectronic integrated circuit using the same, and method for manufacturing optoelectronic integrated circuit 有权
标题翻译：半导体发光元件，使用其的光电集成电路以及制造光电集成电路的方法
公开(公告)号：JP2008205006A
公开(公告)日：2008-09-04
申请号：JP2007036328
申请日：2007-02-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HISAMOTO MASARU , SAITO SHINICHI , KIMURA SHINICHIRO
IPC分类号： H01L33/16 , G02B6/42 , H01L33/34 , H01L33/44
CPC分类号： H01L27/15 , G02B6/13 , G02B6/43 , H01L33/02 , H01L33/34
摘要： PROBLEM TO BE SOLVED: To provide a highly efficient light-emitting element including, as a basic structural element, a group IV semiconductor material such as silicon or equivalent germanium on a substrate formed of silicon using the ordinary silicon process and also provide a structure of highly efficient waveguide and a method for manufacturing the same. SOLUTION: The light-emitting element is provided with a first electrode to which electrons are injected, a second electrode to which holes are injected, and a light-emitting part that is electrically connected to the first electrode and the second electrode. The light-emitting part is formed of single crystal silicon. The light-emitting part includes a first surface (upper surface) and a second surface (lower surface) in opposition to the first surface. The plane orientation of the first and second surfaces is set to the plane (100). The light-emitting part in the direction orthogonally crossing the first and second surfaces is formed thinner and a material having high refractive index is arranged in the periphery of the thin-film light-emitting part. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种高效率的发光元件，其包括作为基本结构元件的诸如硅或等价锗的IV族半导体材料在使用普通硅工艺的由硅构成的衬底上，并且还提供高效波导的结构及其制造方法。解决方案：发光元件设置有注入电子的第一电极，注入空穴的第二电极和与第一电极和第二电极电连接的发光部。发光部由单晶硅形成。发光部分包括与第一表面相对的第一表面（上表面）和第二表面（下表面）。第一和第二表面的平面取向被设定为平面（100）。与第一和第二表面正交的方向上的发光部分形成得更薄，并且在薄膜发光部分的周围设置具有高折射率的材料。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2006351173A SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS 审中-公开
公开(公告)号：JP2006351173A
公开(公告)日：2006-12-28
申请号：JP2006164272
申请日：2006-06-14
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA HITOSHI , AOKI MASAKAZU , KIMURA SHINICHIRO , NODA HIROMASA , SEKIGUCHI TOMONORI
IPC分类号： G11C11/407 , G06F1/26 , G11C11/408 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus equipped with a stably operated internal power supply circuit or the like. SOLUTION: This apparatus is provided with a power supply circuit operated by a power supply voltage from the outside to form an internal voltage, and an internal circuit to which the internal voltage is applied. A variable impedance means is provided between the output voltage of a charge pump circuit and the internal voltage. A differential amplifying circuit controls the variable impedance means so that a reference voltage corresponding to the internal voltage is compared with the internal voltage and the both are coincident with each other. A power supply circuit is constituted of a first power supply circuit for forming a voltage having a polarity same as that of the voltage supplied from the outside and a second power supply circuit for forming a voltage having a polarity different from the voltage supplied from the out side. The output voltage of the charge pump circuit of the first power supply circuit is applied to an N-well having a P-well forming elements constituting an internal circuit formed therein. The output voltage generated by the charge pump circuit of the second power supply circuit is used also as a substrate back-bias voltage applied to the P-well having the elements constituting the internal circuit formed therein. COPYRIGHT: (C)2007,JPO&INPIT

9. 发明专利

JP2005142484A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005142484A
公开(公告)日：2005-06-02
申请号：JP2003379851
申请日：2003-11-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SEKIGUCHI TOMOKO , KIMURA SHINICHIRO , YAMADA RENICHI , WATANABE KIKUO , MIKI HIROSHI , TAKEDA KENICHI
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66659 , H01L27/10855 , H01L27/10873 , H01L27/10894 , H01L29/1079 , H01L29/6656 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having DRAM with small variation in threshold voltage of a MISFET in a memory cell and superior charge holding characteristics of a capacitor, and to provide the manufacturing method of the semiconductor device.
SOLUTION: In the structure of an unsymmetrical diffusion layer, impurity concentration of n-type semiconductor region and p-type semiconductor region on the data line side is relatively made higher than impurity concentration of n-type semiconductor region and p-type semiconductor region on the capacitor side. Before a light oxidation process, an anti-oxidation film is formed on the side wall of a gate electrode so that oxidation of the side wall of the gate electrode can be restricted and a variation of film thickness of the film formed on the side wall can be made small.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有存储单元中MISFET的阈值电压变化小且具有优异的电容保持特性的DRAM的半导体器件，并提供半导体器件的制造方法。解决方案：在不对称扩散层的结构中，数据线侧的n型半导体区域和p型半导体区域的杂质浓度相对高于n型半导体区域和p型的杂质浓度电容器侧的半导体区域。在轻氧化处理之前，在栅电极的侧壁上形成抗氧化膜，从而可以限制栅极侧壁的氧化，并且可以限制形成在侧壁上的膜的膜厚变化做得小版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2003188280A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2003188280A
公开(公告)日：2003-07-04
申请号：JP2001382942
申请日：2001-12-17
申请人： HITACHI LTD , ELPIDA MEMORY INC
发明人： TAKAURA NORIKATSU , TAKEMURA RIICHIRO , MATSUOKA HIDEYUKI , KIMURA SHINICHIRO , ASAKURA HISAO , NAGAI AKIRA , YAMADA SATORU
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/092 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce unevenness of a threshold voltage of a MISFET or MISFET pair for constituting, for example, a sense amplifier. SOLUTION: In a logic circuit region having a logic circuit necessary to drive a memory cell such as a sense amplifier circuit or the like, n-type active regions nw1, nw2 not having a gate electrode are disposed at both ends of active regions (nwp1, nwp2) having p-channel MISFET pair for constituting the sense amplifier, and (L4-L5), (L6-L5) and (L4-L6), wherein L4 is the distance between the region nwp1 and the region nw1, L6 is the distance between the region newp2 and the region nw2, and L5 is the distance between the region nwp1 and the region nwp2, are set substantially '0' or less than twice a minimum processing size. As a result, the unevenness of the shape of an element isolation groove in the L4, L5 and L6 is reduced, and a threshold voltage difference of the MISFET pair can be suppressed. COPYRIGHT: (C)2003,JPO

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