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1. 发明专利

JP2012069585A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012069585A
公开(公告)日：2012-04-05
申请号：JP2010211078
申请日：2010-09-21
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： AOKI MAYU , TAKEDA KENICHI , HOZAWA KAZUYUKI
IPC分类号： H01L25/065 , H01L21/60 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L25/50 , H01L23/481 , H01L23/562 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/29 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2224/0401 , H01L2224/05547 , H01L2224/05557 , H01L2224/08121 , H01L2224/11462 , H01L2224/1148 , H01L2224/11602 , H01L2224/13019 , H01L2224/13147 , H01L2224/13565 , H01L2224/13582 , H01L2224/13647 , H01L2224/13687 , H01L2224/1403 , H01L2224/14051 , H01L2224/26122 , H01L2224/2919 , H01L2224/73104 , H01L2224/81007 , H01L2224/81203 , H01L2224/83007 , H01L2224/83203 , H01L2224/83862 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2924/00013 , H01L2924/01029 , H01L2924/10253 , H01L2924/14 , H01L2224/11 , H01L2924/00014 , H01L2924/04941 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To minimize voids on the adhesive surfaces of two silicon wafers in a semiconductor device where two silicon wafers are superimposed and bonded, and bump electrodes formed on the two silicon wafers, respectively, are connected electrically.SOLUTION: On the adhesive surfaces of a silicon wafer 10A and a silicon wafer 10B, cavities 23 resulting from recesses 22 formed in the surface of a buried conductive film 21 are formed. End of the cavity 23 extends to the periphery of the adhesive surfaces of the wafers 10A, 10B. Since air trapped in the adhesive surfaces escapes to the outside through the cavities 23, generation of voids in the adhesive surfaces can be minimized.
摘要翻译：要解决的问题：为了最小化两个硅晶片被叠加和接合的半导体器件中的两个硅晶片的粘合剂表面上的空隙，并且分别在两个硅晶片上形成的凸起电极电连接。解决方案：在硅晶片10A和硅晶片10B的粘合表面上，形成由埋入导电膜21的表面形成的凹部22产生的空腔23。空腔23的端部延伸到晶片10A，10B的粘合剂表面的周边。由于夹在粘合剂表面中的空气通过空腔23逸出到外部，所以可以使粘合剂表面中的空隙的产生最小化。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2008166360A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2008166360A
公开(公告)日：2008-07-17
申请号：JP2006351721
申请日：2006-12-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TONOMURA OSAMU , MIKI HIROSHI , SEKIGUCHI TOMOKO , TAKEDA KENICHI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L28/65 , H01L27/10852
摘要： PROBLEM TO BE SOLVED: To suppress diffusion of ruthenium, or the like, into hafnium oxide, or the like, in a DRAM capacitor using ruthenium or ruthenium oxide into an upper electrode and hafnium dioxide or zirconium oxide into an insulating film. SOLUTION: Diffusion of ruthenium or the like into hafnium dioxide, or the like, is suppressed by inserting tantalum pentaoxide or niobium oxide, having a dielectric constant larger than that of the insulating film as a cap layer insulating film into the interface between the upper electrode of ruthenium or ruthenium oxide and the insulating film of hafnium dioxide or zirconium oxide. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了在使用钌或氧化钌的DRAM电容器中将钌等的扩散抑制到氧化铪等中，进入上电极和二氧化铪或氧化锆成为绝缘膜。解决方案：通过将介电常数大于绝缘膜的介电常数的五氧化二钽或铌氧化物作为覆盖层绝缘膜，将钌等扩散到二氧化铪等中被抑制在钌或氧化钌的上电极和二氧化铪或氧化锆的绝缘膜。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007243206A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007243206A
公开(公告)日：2007-09-20
申请号：JP2007104390
申请日：2007-04-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KONDO SEIICHI , HONMA YOSHIO , SAKUMA NORIYUKI , TAKEDA KENICHI , HINODE KENJI
IPC分类号： H01L21/304 , B24B37/00 , C09K3/14
摘要： PROBLEM TO BE SOLVED: To provide a polishing technology which prevents scratch, peeling, dishing, and erosion, and does not need complex cleaning process and complex abrasive powder supply/disposal apparatus, to reduce cost of expendable supplies such as abrasive powder, polishing cloth. SOLUTION: A metal film 21 formed on an insulating film 23 having grooves is polished with the polishing cloth by using a polishing solution which includes a substance making an oxidizer and an oxide water-soluble, does not include abrasive grains substantially, and polish solution that shows a property of a corrosion condition for a metal film. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供防止划伤，剥离，凹陷和侵蚀的抛光技术，并且不需要复杂的清洁工艺和复杂的磨料粉末供应/处理设备，以降低诸如磨料粉末的消耗品的成本，抛光布。解决方案：通过使用包括制造氧化剂和氧化物水溶性的物质的抛光溶液，用抛光布抛光形成在具有槽的绝缘膜23上的金属膜21，基本上不包括磨料颗粒，以及抛光溶液，其显示金属膜的腐蚀条件的性质。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005142484A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005142484A
公开(公告)日：2005-06-02
申请号：JP2003379851
申请日：2003-11-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SEKIGUCHI TOMOKO , KIMURA SHINICHIRO , YAMADA RENICHI , WATANABE KIKUO , MIKI HIROSHI , TAKEDA KENICHI
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66659 , H01L27/10855 , H01L27/10873 , H01L27/10894 , H01L29/1079 , H01L29/6656 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having DRAM with small variation in threshold voltage of a MISFET in a memory cell and superior charge holding characteristics of a capacitor, and to provide the manufacturing method of the semiconductor device.
SOLUTION: In the structure of an unsymmetrical diffusion layer, impurity concentration of n-type semiconductor region and p-type semiconductor region on the data line side is relatively made higher than impurity concentration of n-type semiconductor region and p-type semiconductor region on the capacitor side. Before a light oxidation process, an anti-oxidation film is formed on the side wall of a gate electrode so that oxidation of the side wall of the gate electrode can be restricted and a variation of film thickness of the film formed on the side wall can be made small.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有存储单元中MISFET的阈值电压变化小且具有优异的电容保持特性的DRAM的半导体器件，并提供半导体器件的制造方法。解决方案：在不对称扩散层的结构中，数据线侧的n型半导体区域和p型半导体区域的杂质浓度相对高于n型半导体区域和p型的杂质浓度电容器侧的半导体区域。在轻氧化处理之前，在栅电极的侧壁上形成抗氧化膜，从而可以限制栅极侧壁的氧化，并且可以限制形成在侧壁上的膜的膜厚变化做得小版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2009302082A Semiconductor device, and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009302082A
公开(公告)日：2009-12-24
申请号：JP2008151225
申请日：2008-06-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUJIWARA TAKESHI , IMAI TOSHINORI , TAKEDA KENICHI , SHIMAMOTO HIROMI
IPC分类号： H01L21/822 , H01L21/3205 , H01L23/52 , H01L27/04
CPC分类号： H01L23/5228 , H01L27/0688 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a metal resistor element from being oxidized to increase a resistance value, and preventing increase of parasitic capacitance between metal wire layers without complicating a fabrication process; and a manufacturing method of the same. SOLUTION: This semiconductor device includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface thereof; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from those of the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够防止金属电阻元件被氧化以增加电阻值并且防止金属线层之间的寄生电容增加而不使制造工艺复杂化的半导体器件; 及其制造方法。解决方案：该半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在其上表面上的上表面氧化防止绝缘膜; 以及仅在金属电阻元件的侧面附近形成的侧面抗氧化绝缘膜，通过在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上进行各向异性蚀刻，以及上表面的氧化防止绝缘膜。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2009021509A Semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009021509A
公开(公告)日：2009-01-29
申请号：JP2007184614
申请日：2007-07-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKEDA KENICHI , FUJIWARA TAKESHI , IMAI TOSHINORI
IPC分类号： H01L21/822 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L23/52 , H01L27/04
CPC分类号： H01C17/12 , H01C7/006 , H01L23/5228 , H01L27/016 , H01L28/20 , H01L2924/0002 , Y10T29/49099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology for obtaining a semiconductor device with a resistance element having a low parasitic capacity and a small change in resistance value during heat treatment. SOLUTION: In a reactive DC sputtering method using tantalum as a sputtering target material and argon-nitrogen mixed gas as sputtering gas, a first resistance layer 5a consisting of a tantalum nitride film and having a thickness of 20 nm and a nitrogen concentration of less than 30 atom% and a second resistance layer 5b consisting of a tantalum nitride film and having a thickness of 5 nm and a nitrogen concentration of 30 atom% or more are formed in sequence. Then, the first and second resistance layers 5a, 5b are processed to form a resistance element R1. An upper region having a nitrogen concentration of 30 atom% or more is provided for reducing the resistance variation of the resistance element R1 down to less than 1% even when thermal load is given thereto in a wiring process. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在热处理期间获得具有低寄生电容和电阻值变化小的电阻元件的半导体器件的技术。解决方案：在使用钽作为溅射靶材料和氩 - 氮混合气体作为溅射气体的反应型DC溅射法中，由氮化钽膜构成的厚度为20nm的第一电阻层5a和氮浓度小于30原子％的第二电阻层5b和由氮化钽膜构成的厚度为5nm，氮浓度为30原子％以上的第二电阻层5b依次形成。然后，对第一和第二电阻层5a，5b进行处理以形成电阻元件R1。提供氮浓度为30原子％以上的上部区域，即使在布线处理中给予热负荷，也可以将电阻元件R1的电阻变化降低到小于1％。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2013004715A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013004715A
公开(公告)日：2013-01-07
申请号：JP2011134003
申请日：2011-06-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOZAWA KAZUYUKI , TAKEDA KENICHI , AOKI MAYU , HANAOKA HIROKO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/94 , H01L21/486 , H01L21/561 , H01L23/147 , H01L23/49827 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/1469 , H01L2224/0346 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05611 , H01L2224/10135 , H01L2224/10165 , H01L2224/1146 , H01L2224/1147 , H01L2224/13013 , H01L2224/13109 , H01L2224/13147 , H01L2224/13155 , H01L2224/16146 , H01L2224/17181 , H01L2224/81141 , H01L2224/81191 , H01L2224/81203 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2224/11 , H01L2924/00014 , H01L2924/014 , H01L2224/81
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which thinning and flattening of a substrate can be carried out in the state of a chip just cut from a semiconductor wafer, and a through electrode and a bump electrode can be formed on the flat surface, and to provide a manufacturing method therefor.SOLUTION: When connecting a semiconductor chip CHP1 with a semiconductor wafer 1W, a connection surrounding the internal region (bump electrode formation region) in the semiconductor chip CHP1 is provided along the outer periphery in the semiconductor chip CHP1. More specifically, on the surface of a chip region of the semiconductor wafer 1W, a plurality of concave bump electrode receiving parts BRU, and a concave CAU surrounding the plurality of concave bump electrode receiving parts BRU are formed. When the semiconductor chip CHP1 is mounted on the semiconductor wafer 1W and fixed, a plurality of bump electrodes BMP are inserted, respectively, into the plurality of bump electrode receiving parts BRU and a convex VEU is inserted into the concave CAU.
摘要翻译：要解决的问题：提供一种半导体器件，其中可以在刚从半导体晶片切割的芯片的状态下进行衬底的薄化和平坦化，并且可以形成贯通电极和凸块电极平坦表面，并提供其制造方法。解决方案：当将半导体芯片CHP1与半导体晶片1W连接时，沿着半导体芯片CHP1的外周设置围绕半导体芯片CHP1的内部区域（突起电极形成区域）的连接。更具体地，在半导体晶片1W的芯片区域的表面上，形成有多个凹凸电极接收部BRU和围绕多个凹凸电极接收部BRU的凹状CAU。当将半导体芯片CHP1安装在半导体晶片1W上并固定时，将多个凸块电极BMP分别插入到多个凸块电极接收部分BRU中，并且将凸形VEU插入到凹入CAU中。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2007071737A Flow sensor 有权
标题翻译：流量传感器
公开(公告)号：JP2007071737A
公开(公告)日：2007-03-22
申请号：JP2005259902
申请日：2005-09-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKUMA NORIYUKI , YAMAMOTO NAOKI , TAKEDA KENICHI , FUKUDA HIROSHI
IPC分类号： G01F1/692 , G01F1/69
CPC分类号： G01F1/6845 , G01F1/699 , G01P5/10
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of providing a flow sensor of high sensitivity, by forming a metal film having relatively high TCR via an insulating film on a semiconductor substrate. SOLUTION: A measuring element of a thermal type fluid flow sensor includes: a heating resistor 3 constituted of the first metal film; a temperature detecting resistor (upstream temperature detecting resistor 4a and downstream temperature detecting resistor 4b); and an air temperature detecting resistor 5. The first metal film is formed of an α-Ta film having the resistivity of three times or less of that in a Ta ingot obtained with deposition by a spattering method on an amorphous film 9 containing metal. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过在半导体衬底上通过绝缘膜形成具有相对较高TCR的金属膜，提供能够提供高灵敏度的流量传感器的技术。解决方案：热式流体流量传感器的测量元件包括：由第一金属膜构成的加热电阻器3; 温度检测电阻器（上游温度检测电阻器4a和下游温度检测电阻器4b）; 和空气温度检测电阻器5.第一金属膜由具有通过溅射法沉积得到的Ta锭中的电阻率为包含金属的非晶膜9上的电阻率的三倍以下的α-Ta膜形成。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2004072099A Polishing method 审中-公开
公开(公告)号：JP2004072099A
公开(公告)日：2004-03-04
申请号：JP2003205241
申请日：2003-08-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KONDO SEIICHI , HONMA YOSHIO , SAKUMA NORIYUKI , TAKEDA KENICHI , HINODE KENJI
IPC分类号： B24B37/00 , H01L21/304 , H01L21/306
摘要： PROBLEM TO BE SOLVED: To provide a polishing technique which inhibits scratching, peeling off, dishing and erosion, and requires no complex cleaning process nor abrasive agent supplying/ treating device so that it curbs the cost of consumable supplies such as a polishing agent and a polishing cloth, etc. SOLUTION: A metal film 21 formed on an insulation film 23 having a groove is polished with a polishing liquid which comprises an oxidizer and a material dissolving an oxide in water, and does not comprise abrasive particles. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2007059761A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007059761A
公开(公告)日：2007-03-08
申请号：JP2005245492
申请日：2005-08-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKEDA KENICHI , FUJIWARA TAKESHI , IMAI TOSHINORI
IPC分类号： H01L21/822 , H01L21/768 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with an MIM capacitor capable of utilizing a wiring region directly under the MIM capacitor as a wiring, and capable of preventing the number of wiring layers and an IC chip area from increasing, in the spatially constituted MIM capacitor capable of raising a capacitance density, and to provide a method of manufacturing the semiconductor device. SOLUTION: The method comprises the steps of forming an interlayer dielectric 301 so as to cover a lower layer wiring; forming an opening whose height is smaller than a film thickness of the interlayer dielectric on the basis of a top face of the lower layer wiring to the interlayer dielectric; and forming the MIM capacitor constituted by an upper electrode 204, a capacitance film 401, and a lower electrode 203 so as to cover the opening. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决方案：为了提供一种配备有能够利用MIM电容器正下方的布线区域的MIM电容器的半导体器件作为布线，并且能够防止布线层数量和IC芯片面积增加，在能够提高电容密度的空间构成的MIM电容器中，提供半导体装置的制造方法。解决方案：该方法包括以下步骤：形成层间电介质301以覆盖下层布线; 基于层间电介质的下层布线的顶面，形成高度小于层间电介质的膜厚的开口部; 以及形成由上电极204，电容膜401和下电极203构成的MIM电容器以覆盖开口。版权所有（C）2007，JPO＆INPIT

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