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    • 3. 发明专利
    • SEMICONDUCTOR INTEGRATED CIRCUIT
    • JPH08160092A
    • 1996-06-21
    • JP29743994
    • 1994-11-30
    • HITACHI LTDHITACHI COMPUTER ENG
    • HIROSE TAKESHINAGAYA YUJIHASHIMOTO TAKASHIYOSHINAGA MAKIHATANAKA NORIAKISOGA YUJIMORIYA ATSUSHI
    • G01R31/26G01R31/02H01L21/66H01L21/822H01L27/04
    • PURPOSE: To surely detect head opening abhormality by counting the time during which the voltage between head terminals is lower than a prescribed slicing level and comparing the count value with a preset value. CONSTITUTION: When head opening abnormality occurs, a voltage waveform in which the time during which the flyback voltage between head terminals becomes lower than a slicing level becomes longer than that obatined when no head opening abnormality occurs is obtained. A sense circuit detects the voltage waveform and the input transistor Q51 of a buffer circuit 22 is turned on by, for example, making an electric current to flow to the transistor Q51 from an output terminal IUX, Consequently, the output of the circuit 22 becomes 'L' and the differential transistor Q62 of a timer circuit 23 is turned off, and then, a capacity is charged by means of a collector-side transistor Qp62 and the potential at a node N11 rises. When such a state becomes longer than a preset pariod of time, the potential at the node N11 becomes higher than the reference voltage VR3 of a level discriminated circuit 25 and the output of the circuit 24 is inverted to αHβ from αLβ. The output VOPN which latches 25 the output of the circuit 24 changes to αHβ and the head abnormality detecting signal of a logical gate circuit changes. Therefore, the head opening abnormality can be detected surely.
    • 5. 发明专利
    • Integration circuit
    • 集成电路
    • JPS61128379A
    • 1986-06-16
    • JP24961584
    • 1984-11-28
    • Hitachi LtdHitachi Medical Corp
    • MORIYA ATSUSHIMAIO KENJI
    • G06G7/186
    • PURPOSE: To compensate offset voltage or drift by connecting a device for holding the reverse voltage of the offset voltage to one input terminal of an integrating amplifier and setting up said device by using a part of the discharge period of an integrating capacitor.
      CONSTITUTION: At the discharge of the integrating capacitor 2, an input offset voltage e
      of is outputted to an output eθ and the e
      of is held in a holding capacitor 10 in the arrow direction. When switches 7, 8 are opened and a switch 9 is closed, the capacitor 10 is connected to the non-inversional input of the integrat ing amplifier 3. However, the holding voltage of the capacitor 10 is the reverse polarity against the e
      of , so that the offset voltages of the inversional and non- inversional input terminals of the amplifier 3 are equally compensated to zero and the output eθ is set up precisely to 0V through a switch 4. Then, a switch 6 is opened, and during the application of an input pulse, integration is executed, an offset error at the start of integration, an integrating error at the time of integration and a droop error at the holding of voltage can be removed.
      COPYRIGHT: (C)1986,JPO&Japio
    • 目的:通过连接用于保持偏移电压的反向电压的器件与积分放大器的一个输入端子并通过使用积分电容器的放电周期的一部分来设置所述器件来补偿失调电压或漂移。 构成:在积分电容器2的放电时,将输入偏移电压eof输出到输出etheta,eof沿箭头方向保持在保持电容器10中。 当开关7,8断开并且开关9闭合时,电容器10连接到积分放大器3的非反相输入端。然而,电容器10的保持电压与eof相反极性,因此 放大器3的反相和非反相输入端的偏移电压被均等地补偿为零,并且通过开关4将输出etheta精确地设置为0V。然后,开关6断开,并且在应用 输入脉冲,积分,积分开始时的偏移误差,积分时的积分误差以及保持电压时的下垂误差。
    • 6. 发明专利
    • Analog digital converter for x-ray ct equipment
    • X射线CT设备的模拟数字转换器
    • JPS6177431A
    • 1986-04-21
    • JP19853784
    • 1984-09-25
    • Hitachi LtdHitachi Medical Corp
    • HAYASHI SHINICHIMAIO KENJIMORIYA ATSUSHI
    • H03M1/56A61B6/03G01T1/17H03M1/58
    • PURPOSE: To decrease the number of effective bits of a digital output by comparing a polygonal ramp voltage with an input voltage and shifting down the content of count based on the weight of a constant electric current source at each switching of the polygonal line voltage for count.
      CONSTITUTION: A polygonal ramp voltage having a gradient in response to constant current source is generated from an integration device comprised of the constant current source i
      0 , 4i
      0 , 16i
      0 limited with a prescribed accuracy, a switch group switching sequentially them, an operational amplifier OP and a capacitor C. The ramp voltage and input voltages V
      1 ∼V
      n are compared with each other by comparators C
      1 ∼C
      n . A counter K counts a clock CLK to generate a digital value corresponding to the ramp voltage, and when the input voltages V
      1 ∼V
      n are coincident with the ramp voltage at the comparators C
      1 ∼C
      n , the content of the counter K is set to registers R
      1 ∼R
      n . In switching the polygonal line voltage, the content of the counter K is shifted down by using a shift signal SFT based on the weight of the constant current source, inputted to the registers R
      1 ∼R
      n to decrease the total number of bits.
      COPYRIGHT: (C)1986,JPO&Japio
    • 目的:通过将多边形斜坡电压与输入电压进行比较来减少数字输出的有效位数,并在每次切换多边形线电压时,根据恒定电流源的重量将计数的内容向下移动 。 构成:从由恒定电流源i0,4I0,16i0组成的积分装置产生一个响应于恒定电流源具有梯度的多边形斜坡电压,其以规定的精度限制,开关组依次切换它们,运算放大器OP和 电容器C.斜坡电压和输入电压V1-Vn通过比较器C1-Cn相互比较。 计数器K计数时钟CLK以产生对应于斜坡电压的数字值,并且当输入电压V1-Vn与比较器C1-Cn处的斜坡电压一致时,计数器K的内容被设置为寄存器R1 -Rn。 在切换折线电压时,通过使用基于恒定电流源的权重的移位信号SFT将计数器K的内容向下移位,输入到寄存器R1-Rn以减少总位数。
    • 7. 发明专利
    • ANALOG/DIGITAL CONVERTER
    • JPS60112326A
    • 1985-06-18
    • JP21946283
    • 1983-11-24
    • HITACHI LTDHITACHI MEDICAL CORP
    • HAYASHI SHINICHIMAIO KENJIMORIYA ATSUSHI
    • H03M1/56H03M1/12
    • PURPOSE:To attain effectively the desired accuracy for a current source of a lamp voltage generator by comparing the input voltage with the lamp voltage given from the generator for broken line-shaped lamp voltage which contains switch groups and an integrator and extracting the digital output corresponding to each input voltage with the accuracy necessary for each register. CONSTITUTION:A switch S0 is opened at a time point t0 and a switch S1 is closed for a section of t1. The lamp voltage (y) rises up with a slope proportional to the courrent value I1 by an integration circuit (OP and C). A counter K1 starts counting with a clock CLK and produces the digital value corresponding to the lamp voltage value. the contents of a counter K are set to register groups L1-Ln when coincidence is obtained between the input voltages V1-Vn and the lamp voltage respectively. The switch S1 is opened at a time point (t0+t1) and the switch S2 is closed for a section of t2. The voltage (y) rises up in proportion to the value I2, and the counter K1 is shifted down by a shift signal SFT by an amount equivalent to the difference of weight between current values I1 and I2.
    • 8. 发明专利
    • Control system of analog multiplexer
    • 模拟多路复用器控制系统
    • JPS59147534A
    • 1984-08-23
    • JP1981483
    • 1983-02-10
    • Hitachi LtdHitachi Medical Corp
    • MAIO KENJIMORIYA ATSUSHI
    • H03K17/00H03K17/62
    • H03K17/62
    • PURPOSE:To decrease the switching time by controlling the system so that one channel signal is outputted from a nonselected multiplexer when many analog signals are changed over and read out successively by many analog multiplexers and the switches at the poststage. CONSTITUTION:When an analog multiplexer MPX61 is in use, only a selecting signal 41 is at ''1'' and others are at ''0''. Thus, the switch selecting signals A-D of the MPX61 are at the same level as a signal 3 by the operation of a gate circuit 7 but other selecting signals are at ''0'' and the switch of the 1st channel is selected. Since switches 22-24 of the next and succeeding stages are opened, only an output of the 1st block appears on an output line 71. Since the 1st channel of the nonselected MPXes is selected in this way, the signal potential of the 1st channel of each block is charged in output parasitic capacitance, the charge/ discharge current at switching does not almost exist and high-speed switching is attained.
    • 目的:通过控制系统来减少切换时间,以便当许多模拟信号由许多模拟多路复用器和后台的开关连续读出时,从非选择的多路复用器输出一个通道信号。 构成:当使用模拟多路复用器MPX61时,只有选择信号41处于“1”,而其他处于“0”。 因此,通过门电路7的操作,MPX61的开关选择信号A-D处于与信号3相同的电平,但是其他选择信号为“0”,并且选择第一通道的开关。 由于下一级和后级的开关22-24打开,所以在输出线71上仅出现第一块的输出。由于以这种方式选择了非选择的MPX的第一通道,所以第一通道的信号电位 每个块在输出寄生电容中充电,开关中的充电/放电电流几乎不存在,并且实现了高速切换。