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1. 发明专利

JPS5897731A INPUT AND OUTPUT CONTROLLING SYSTEM FOR LOGICAL INTEGRATED CIRCUIT 失效
公开(公告)号：JPS5897731A
公开(公告)日：1983-06-10
申请号：JP19718081
申请日：1981-12-07
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , MAEDA SHIGEMICHI , AKAZAWA TAKASHI , SUGIYAMA SHIZUO , KOIZUMI HARUO
IPC分类号： G06F13/36 , G06F3/00 , G06F13/40 , G06F15/16 , G06F15/177 , G06F15/78
摘要： PURPOSE:To simplify an interface circuit, by stopping an internal clock working mode to a data transfer request given from the outside to an internal register and at the same time producing independently a bus precharge signal. CONSTITUTION:A transfer request code is applied from an external digital computer in the form of a function signal 5, and the chip selecting signal 7 is supplied. Thus a control circuit 16 detects those signals, and the data transfer request signal 32 is fed to a clock generator 19. Then the generator 19 delivers the signal 31 to stop the normal operation and thus stops clocks phi0-phi3. At the same time, the generator 19 delivers a precharge signal 30 to precharge a data bus 4 up to a level 1. The contents of the bus 4 are delivered to an external data bus 3 of an LSI1 with the I/O control signal 35 which is controlled by a timing signal 6 and then read out to a digital computer.

2. 发明专利

DE3033867A1 未知
公开(公告)号：DE3033867A1
公开(公告)日：1981-04-09
申请号：DE3033867
申请日：1980-09-09
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , FUNABASHI TSUNEO , KOIZUMI HARUO
IPC分类号： G06F7/68 , H03K5/00 , H03K5/156
摘要： In a pulse frequency multiplying circuit, a first capacitor charged to a given potential is discharged through a first constant-current circuit during a period corresponding to a pulse width of a reference pulse. Then, the terminal voltage of the first capacitor is applied as a reference voltage to one input terminal of a comparator circuit. A triangle wave voltage formed by alternately discharging a pair of second capacitors charged to a given potential, through a second constant-current circuit with a current value n times that in the first constant-current circuit, is applied to the other input terminal of the comparator circuit. The output from the comparator circuit operates a flip-flop circuit. In accordance with the output signal, the charge/discharge operation of said second capacitors is switched, whereby said flip-flop circuit produces a pulse with a frequency n times that of the reference pulse.

3. 发明专利

DE69736047T2 未知
公开(公告)号：DE69736047T2
公开(公告)日：2006-10-05
申请号：DE69736047
申请日：1997-03-19
申请人： HITACHI LTD
发明人： AOKI MASAMI , KAWADA TOYOSHI , KOIZUMI HARUO
IPC分类号： G09G3/20 , G09G3/288 , G09G3/291 , G09G3/293 , G09G3/296 , G09G3/298
摘要： A plasma-display-panel display apparatus includes a flat display panel having a plurality of address electrodes (21) and a plurality of scanning electrodes (11) extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween. A scanning electrode driver (32) successively supplies scanning pulses to the scanning electrodes(11) with scanning timing, and an address driver (34) supplies address pulses according to display data to the address electrodes (21) in synchronism with the scanning timing. The address electrodes include first and second address electrodes (Ai, Ai+1) disposed adjacent to each other. The address pulse applied to the first address electrode (Ai) rises and the address pulse applied to the second address electrode (Ai+1) falls with a predetermined time difference therebetween.

4. 发明专利

DE69736047D1 未知
公开(公告)号：DE69736047D1
公开(公告)日：2006-07-20
申请号：DE69736047
申请日：1997-03-19
申请人： HITACHI LTD
发明人： AOKI MASAMI , KAWADA TOYOSHI , KOIZUMI HARUO
IPC分类号： G09G3/20 , G09G3/288 , G09G3/291 , G09G3/293 , G09G3/296 , G09G3/298
摘要： A plasma-display-panel display apparatus includes a flat display panel having a plurality of address electrodes (21) and a plurality of scanning electrodes (11) extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween. A scanning electrode driver (32) successively supplies scanning pulses to the scanning electrodes(11) with scanning timing, and an address driver (34) supplies address pulses according to display data to the address electrodes (21) in synchronism with the scanning timing. The address electrodes include first and second address electrodes (Ai, Ai+1) disposed adjacent to each other. The address pulse applied to the first address electrode (Ai) rises and the address pulse applied to the second address electrode (Ai+1) falls with a predetermined time difference therebetween.

5. 发明专利

JPS6398118A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6398118A
公开(公告)日：1988-04-28
申请号：JP24293886
申请日：1986-10-15
申请人： HITACHI LTD
发明人： KOIZUMI HARUO , YAMAGUCHI NOBORU , NOGUCHI YOSHIKI , SATO TSUKASA , HAGIWARA YOSHIMUNE
IPC分类号： H01L21/66 , G01R31/302 , H01L21/02
摘要： PURPOSE:To enable reducing the analysis time of the defect of a semiconductor integrated circuit by forming a mark which can be used for the retrieval of the layout pattern of a signal which is to be observed by such as an electron beam tester. CONSTITUTION:A potential difference is given to upper layer metals 4 and 5 by an alternating current power source 8 via a wiring 9. In such a state, if the electron beam 14 of a scanning type electron microscope is irradiated, the emission of a secondary electron according to the potential difference is observed so a mark can be observed even by an electron beam tester as a good contrast image. The mark which can be observed even by such an electron beam tester is provided one each in approx. one region which can be observed in one field of view of the electron beam tester. This makes at least one mark pattern exist in a region which is observed by the electron beam tester so to find the pattern of a signal which is to be observed is made easy in reference to the mark pattern.

6. 发明专利

JPS625446A METHOD AND DEVICE FOR CONTROLLING MICROPROCESSOR 失效
公开(公告)号：JPS625446A
公开(公告)日：1987-01-12
申请号：JP14425485
申请日：1985-07-01
申请人： HITACHI LTD
发明人： YAMAGUCHI NOBORU , UCHIYAMA KUNIO , KOIZUMI HARUO , HAGIWARA YOSHIMUNE
IPC分类号： G06F1/00 , G06F1/24 , G06F9/22 , G06F11/28 , G06F15/78
摘要： PURPOSE:To facilitate the debugging of a microprogram and the trouble diagnosis of a microprocessor by generating a stop signal in synchronization with a clock cycle when the stop signal is received from the outside. CONSTITUTION:A stop/execution control circuit 7 receives the 'H' of the STOP signal impressed on an input terminal 24 in synchronization with internal clocks phi1 and phi2 by means of D-FFs 33 and 34, transmits the FRZ signal of 'L' from a NAND circuit 41 and causes the microprocessor in a stop state. Thus the microprocessor can be stopped in the boundary of any clock cycle. As a result the trouble diagnosis of the microprocessor and the debugging of the microprogram can be substantially facilitated.

7. 发明专利

JPS61210655A LAYOUT METHOD FOR LOGIC LSI 失效
公开(公告)号：JPS61210655A
公开(公告)日：1986-09-18
申请号：JP5050285
申请日：1985-03-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NOGUCHI YOSHIKI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , KOIZUMI HARUO , MASUDA HIROYUKI
IPC分类号： H01L21/3205 , G06F17/50 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/02 , H01L27/04
摘要： PURPOSE:To arrange a random logic gate part, which is formed in a logic LSI, regularly without deteriorating circuit characteristics, by making the wiring lengths not so long, and making the numbers of possible wirings in the longitudinal and lateral directions approximately equal. CONSTITUTION:For power supply to a control part, main power source lines 25 and 27 and main grounding lines 26 and 28 are arranged by using diffused-layer wirings or upper layer wirings in the direction in parallel with a ROM 23 and an operating circuit 24. Logic gate columns 29 and 30 are formed in the direction perpendicular to the main power source lines and the main grounding lines. Power source lines 31 and 33 and grounding lines 32 and 34 for the gate columns are formed by lower- layer wirings and connected to the main power-source lines and the main grounding lines. In this constitution, the lengths of the power source lines and the grounding lines for the gate columns can be specified by the intervals among the main power source lines and the main grounding lines. The control part becomes long in the lateral direction, which is in parallel with the ROM 23 and the operating circuit 24. Therefore, the number of upper layer metal wirings 35 and the like, which can be arranged between the gate columns becomes approximately equal to the number of upper-layer wirings 36 and the like, which can be laid out on the gate columns.

8. 发明专利

JPS6375578A FAULT DIAGNOSING METHOD FOR LOGIC CIRCUIT 失效
公开(公告)号：JPS6375578A
公开(公告)日：1988-04-05
申请号：JP21916986
申请日：1986-09-19
申请人： HITACHI LTD
发明人： YAMAGUCHI NOBORU , NAKAMURA HIDEO , HAGIWARA YOSHIMUNE , KOIZUMI HARUO , SATO TSUKASA
IPC分类号： H01L21/66 , G01R31/28 , G01R31/3183 , G06F11/22 , H01L21/822 , H01L27/04
摘要： PURPOSE:To shorten a fault diagnostic time by irradiating a specific point of a logic circuit to be diagnosed with an electron beam and finding variation of the signal of the part with time. CONSTITUTION:An LST tester 6 is supplied with a test pattern from a computer device 7 and transduces it into an electric signal, which is inputted to the circuit 1 to be diagnosed. The signal of the output terminal of the circuit 1 is observed and inputted as a logical value sequence. An electron beam tester 3 irradiates the observation point with the electron beam 2 and detects the quantity of secondary electrons generated there. Then an observation signal processor 4 converts waveform data obtained by the tester 3 at the observation point into logic information, which is set out to the device 7. The device 7 compares the local value sequence, i.e. expected logical value sequence obtained at an output terminal or specific observation point by the logical simulation of the circuit 1 with an actually detected logical value sequence to detect the signal of a defect in operation. Then a diagnose is taken by tracking only the path of the defect signal, i.e. a path where a fault is predicted, so the diagnosis is easily taken in a short period as compared with the inspection of the whole large-scale integrated circuit.

9. 发明专利

JPS6350031A TROUBLE DIAGNOSTIC FOR LOGIC INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6350031A
公开(公告)日：1988-03-02
申请号：JP19288486
申请日：1986-08-20
申请人： HITACHI LTD
发明人： YAMAGUCHI NOBORU , NAKAMURA HIDEO , HAGIWARA YOSHIMUNE , SATO TSUKASA , KOIZUMI HARUO
IPC分类号： G01R31/302 , G01R31/28 , H01L21/66
摘要： PURPOSE:To diagnose trouble quickly and precisely by detecting the input/output signal row of a functional block for a logic IC during operation in a noncontact manner, conducting logic simulation by an input signal row obtained and analyzing mismatch information with a noncontact output signal row. CONSTITUTION:A functional block 2 for an IC chip 1 during operation is irradiated with electron beams, and signal potential is observed 3, and converted 4 into logic information. Conversion timing is displayed by phase difference with a fundamental clock, and indicated by a general purpose computer. Relative movement is acquired from the absolute coordinates where mask information existing in the computer 7 is obtained, and the shifting of a sample base and a beam deflection angle are controlled, thus determining 5 an observation point. A general purpose tester 6 outputs test information memorized to the IC 1 according to timing control information. The computer 7 stores test information, the mask pattern information of the chip 1 and logic connection information, and has a program, from which the positional coordinates of a signal line are acquired, and a logic simulator. According to the constitution, troubles can be diagnosed rapidly by predetermined operation.

10. 发明专利

JPS58105354A COMPUTER CONTROLLING SYSTEM 失效
公开(公告)号：JPS58105354A
公开(公告)日：1983-06-23
申请号：JP20320981
申请日：1981-12-16
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OGIWARA YOSHIMUNE , ISHIZUKA KOUHEI , KOBAYASHI MASAHITO , YAJIMA YOSHIYUKI , KOIZUMI HARUO
IPC分类号： G06F9/32 , G06F9/38 , G06F11/28
摘要： PURPOSE:To eliminate leaving a jump instruction, etc. at an instruction register without increasing the number of circuits when an address is set from outside, by setting the address data transferred to a data bus also to an instruction register. CONSTITUTION:An address is set to a program counter 14 from a controller 2 to change the working sequence of a program while a computer 1 is functioning with a pipeline control system. In this case, an instruction which is precedingly read out is left at an instruction register 16. If this instruction is equal to a jump instruction, the corresponding address is changed. Therefore it is required to set an instruction code excepting the jump instruction to the register 16. In this example, the numerical value is set to the register 16 as soon as an address is set to the counter 14 via a bus 4.

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