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1. 发明授权

US3560957A Signal conversion systems with storage and correction of quantization error 失效
标题翻译：信号转换系统存储和校正错误
公开(公告)号：US3560957A
公开(公告)日：1971-02-02
申请号：US3560957D
申请日：1967-01-23
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： MIURA TAKEO , IWATA JUNZO
IPC分类号： G06G7/19 , G06J1/00 , H03M1/00 , H04B14/04 , H03K13/04 , H03K13/17
CPC分类号： H03M1/00 , G06G7/1928 , G06J1/00 , H03M1/08 , H04B14/046
摘要： DIGITAL TO ANALOG AND SAMPLE-HOLD CIRCUITS IN WHICH CONVERSION OR QUANTIZATION ERROR GENERATED IN EACH SAMPLING OR CONVERSION INTERVAL IS STORED AND ADDED TO THE NEXT CONSECUTIVE INPUT SIGNAL FOR CONVERSION THEREWITH. THE DIGITAL TO ANALOG CONVERTER INCLUDES A CONVENTIONAL CONVERTER HAVING A CAPACITY OF N BITS, FOR CONVERSION OF THE N MOST SIGNIFICANT BITS OF AN N+I BIT INPUT SIGNAL. THE I UNCONVERTED BITS ARE ADDED IN A FULL ADDER TO THE NEXT DIGITAL INPUT. THE SAMPLE-HOLD DEVICE INCLUDES APPARATUS DIGITAL INPUT. THE SAMPLE-HOLD DEVICE INCLUDES APPARATUS SAMPLED OUTPUT AND THE ANALOG INPUT SIGNAL DURING A FIRST SAMPLING INTERVAL. THE INTEGRATED VALUE IS THEN ADDED TO THE ANALOG INPUT SIGNAL DURING THE NEXT SAMPLING INTERVAL.

2. 发明授权

US3621227A Analog line generator 失效
标题翻译：模拟发电机
公开(公告)号：US3621227A
公开(公告)日：1971-11-16
申请号：US3621227D
申请日：1969-02-03
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： TSUDA JUNJI , IWATA JUNZO , HIRANO CHIKAFUSA
IPC分类号： G06G7/25 , G06G7/30 , G06G7/26 , G06G7/18
CPC分类号： G06G7/25 , G06G7/30
摘要： In an analog line generator for producing a straight line connecting two given points, which comprises an integrator, an adder and a feedback circuit from the integrator to the adder, an improvement comprising the provision of a limiter between the adder and the integrator to realize the line generation with higher accuracy and at higher speed.

3. 发明授权

US3524978A Curve-plotting system with interpolation 失效
标题翻译：具有插值的曲线绘图系统
公开(公告)号：US3524978A
公开(公告)日：1970-08-18
申请号：US3524978D
申请日：1967-08-25
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： MIURA TAKEO , IWATA JUNZO , TSUDA JUNJI
IPC分类号： G06F17/17 , G06G7/30 , G06J1/00 , G06K15/22
CPC分类号： G06K15/22 , G06F17/17 , G06G7/30 , G06J1/00

4. 发明授权

US3522419A Electrical device for compensating a digital execution time in hybrid computer systems and the like 失效
标题翻译：用于补充混合计算机系统中的数字执行时间的电气设备和类似
公开(公告)号：US3522419A
公开(公告)日：1970-08-04
申请号：US3522419D
申请日：1968-05-01
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： MIURA TAKEO , IWATA JUNZO
IPC分类号： G06J1/00 , G06G7/18 , G06J3/00
CPC分类号： G06J1/00

5. 发明专利

DE1474146A1 未知
公开(公告)号：DE1474146A1
公开(公告)日：1969-01-09
申请号：DE1474146
申请日：1964-05-15
申请人： HITACHI LTD
发明人： MIURA TAKEO , IWATA JUNZO
IPC分类号： G06G7/06 , G06G7/40
摘要： 1,071,401. Electric analogue calculating. HITACHI SEISAKUSHO KABUSHIKI KAISHA, and HITACHI DENSHI KABUSHIKI KAISHA. May 14, 1964 [May 15, 1963], No. 20178/64. Heading G4G. In an analogue computer having at least one unit cyclically connected to a number of inputs on a time sharing basis, it is shown that a time delay of is introduced, in the output from the unit, where # = time for computation, T = scanning period, T/n = time interval during which a holding circuit connected to each output from the common unit is correctly following the unit output within one scanning period. In order to compensate for this delay, the signal is time advanced by a corresponding amount. In one method, Fig. 6A, suitable for use when the output from a holding unit H i is fed to an integrator circuit I; a signal equal to kT d times the integrator input is obtained from multiplier P and is added to the integrator output after passing through a sign changer SC. Expressed in terms of a Laplace transformation, the actual input e is (p) is given by and the integrator output is The multiplier circuit P produces an output so that the resultant output e oc (p) obtained from adder A is given by The second term is therefore eliminated resulting in a greater accuracy. In a modification, Fig. 6B, the integration also functions as the sign changer by connecting the output from multiplier P to its input via a capacitor C 2 . When the output from the time-shared unit is not fed to an integrator, Fig. 7 (not shown), the value of the output may be pre-estimated a time T d in the future from the expression where Y 0 is the value sampled immediately prior to time under consideration, Y 1 is its value one period earlier than Y 0 . The complete computer may be one in which partial differential equations are solved by transforming them into difference equations, such as a flight simulator wherein an engine computer carries out the same computation for different engines.

6. 发明专利

GB1007953A Analog multiplier 未知
公开(公告)号：GB1007953A
公开(公告)日：1965-10-22
申请号：GB3757262
申请日：1962-10-04
申请人： HITACHI LTD
发明人： MIURA TAKEO , IWATA JUNZO
IPC分类号： G06G7/164
摘要： 1,007,953. Electric analogue calculating. KABUSHIKI KAISHA HITACHI SEIZAKUSHO. Oct. 4, 1962, No. 37572/62. Heading G4G. An arrangement in which multiplication of two input signals x and y is carried out comprises a squaring circuit which produces an output,proportional to (x + y) 2 when supplied with inputs x and y, two further squaring circuits which produce outputs in proportion to' x 2 and y 2 when supplied with inputs x and y respectively and a subtracting circuit, the circuits being assembled so that multiplication is carried out in accordance with the relation xy = (x + y) 2 - x 2 / 2 - Y 2 /2- A circuit A (Fig. 2) for producing the output (x+y) 2 /2 consists of an arrangement of n diodes D 1 -D n each of which has three resistances connected to its input. One of these resistances, in the series Rb 1 -Rb n is connected to the output terminal of a potentiometer in the corresponding series P 1 -P n fed from a voltage supply -E.-The second, in the series Rx 1 -Rx n , is supplied from the x input and the third, in the series Ry 1 -Ry n , is supplied from the y input. The outputs from the diode arrangement are connected together and applied to the input of a high gain amplifier H across which is a feedback resistance Rf. If the circuit through the first diode D1 only is considered and Ry 1 is made equal to Rx 1 , an output voltage l 0 from the amplifier will be obtained, given by l 0 =Rf/Rx1-(x+y)+Rf/Rb1b i , where b 1 is Rx 1 Rb 1 the voltage setting of the potentiometer P1. This gives a linearly increasing negative voltage of slope and intercept determined by the input resistances and the bias voltage provided X + Y> 0 If a number of such circuits, each associated with one of the diodes D 1 -D n , are combined together then a broken line output characteristic approximating to any desired function may be obtained, and in particular the function (x +y) 2 may be approximated by making the corresponding input resistances in the series Rx 1 -Rx n and Ry n -Ry n respectively equal, making the resistances Rb 1 -Rb n to be the same and setting the bias voltages b 1 , b 2 ... b n to voltages at constant intervals in sequence. Such a circuit A may be used only when the input sum x+y is positive. By reversing the diodes D 1 -D n and the polarity of the bias voltage source E a circuit A1 may be obtained wherein the sum of the inputs must be negative for correct operation. By combining the two circuits A and A1 in parallel all possible input conditions can be allowed for. Similar arrangements B and B1 for deriving the functions X 2 / 2 and y 2 /2 may be set up by omitting unnecessary input resistors in the circuits A and A1. The arrangements A and A1 and two of each of the arrangements B and B1 are combined as shown in Fig. 5 with the inputs x and y both fed to the stages A and A1 and each fed individually to one of the stages B and one of the stages B 1. The outputs from those stages which respond to positive going input sums are connected together on one line l 1 and the outputs from the stages responding to negative going input sums are connected together on a second line l 2 . These two lines feed a high gain amplifier H1 provided with both positive and negative input terminals arranged such that the amplifier output is of the same sign as the input to the negative terminal or of the opposite sign as the input to the positive terminal. The amplifier is provided with a feedback resistance Rf and provides an output proportional to - xy. A suitable operational amplifier consisting essentially of a magnetic amplifier with two opposed control windings is briefly described.

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